Philips 74hc hct190 DATASHEETS

INTEGRATED CIRCUITS

DATA SH EET

For a complete data sheet, please also download:

•The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications

•The IC06 74HC/HCT/HCU/HCMOS Logic Package Information

•The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines

74HC/HCT190

Presettable synchronous BCD
decade up/down counter

Product specification
File under Integrated Circuits, IC06

December 1990

Philips Semiconductors Product specification

Presettable synchronous BCD decade
up/down counter

FEATURES

• Synchronous reversible counting

• Asynchronous parallel load

• Count enable control for synchronous expansion

• Single up/down control input

• Output capability: standard

• ICC category: MSI

GENERAL DESCRIPTION

The 74HC/HCT190 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.

The 74HC/HCT190 are asynchronously presettable
up/down BCD decade counters. They contain four
master/slave flip-flops with internal gating and steering
logic to provide asynchronous preset and synchronous
count-up and count-down operation.

Asynchronous parallel load capability permits the counter
to be preset to any desired number. Information present on
the parallel data inputs (D
and appears on the outputs when the parallel load (PL)
input is LOW. As indicated in the function table, this
operation overrides the counting function.

Counting is inhibited by a HIGH level on the count enable
(CE) input. When CE is LOW internal state changes are
initiated synchronously by the LOW-to-HIGH transition of
the clock input. The up/down (U/D) input signal determines
the direction of counting as indicated in the function table.
The CE input may go LOW when the clock is in either
state, however, the LOW-to-HIGH CE transition must
occur only when the clock is HIGH. Also, the U/D input
should be changed only when either CE or CP is HIGH.

to D3) is loaded into the counter

0

74HC/HCT190

Overflow/underflow indications are provided by two types
of outputs, the terminal count (TC) and ripple clock (RC).
The TC output is normally LOW and goes HIGH when a
circuit reaches zero in the count-down mode or reaches “9”
in the count-up-mode. The TC output will remain HIGH
until a state change occurs, either by counting or
presetting, or until U/D is changed. Do not use the TC
output as a clock signal because it is subject to decoding
spikes. The TC signal is used internally to enable the RC
output. When TC is HIGH and CE is LOW, the RC output
follows the clock pulse (CP). This feature simplifies the
design of multistage counters as shown in Figs 5 and 6.

In Fig.5, each RC output is used as the clock input to the
next higher stage. It is only necessary to inhibit the first
stage to prevent counting in all stages, since a HIGH on
CE inhibits theRC output pulse as indicated in the function
table. The timing skew between state changes in the first
and last stages is represented by the cumulative delay of
the clock as it ripples through the preceding stages. This
can be a disadvantage of this configuration in some
applications.

Fig.6 shows a method of causing state changes to occur
simultaneously in all stages. The RC outputs propagate
the carry/borrow signals in ripple fashion and all clock
inputs are driven in parallel. In this configuration the
duration of the clock LOW state must be long enough to
allow the negative-going edge of the carry/borrow signal to
ripple through to the last stage before the clock goes
HIGH. Since the RC output of any package goes HIGH
shortly after its CP input goes HIGH there is no such
restriction on the HIGH-state duration of the clock.

In Fig.7, the configuration shown avoids ripple delays and
their associated restrictions. Combining the TC signals
from all the preceding stages forms the CE input for a
given stage. An enable must be included in each carry
gate in order to inhibit counting. The TC output of a given
stage it not affected by its own CE signal therefore the
simple inhibit scheme of Figs 5 and 6 does not apply.

December 1990 2

Philips Semiconductors Product specification

Presettable synchronous BCD decade
up/down counter

QUICK REFERENCE DATA

GND = 0 V; T

SYMBOL PARAMETER CONDITIONS

t

/ t

PHL

PLH

f

max

C

I

C

PD

Notes

1. C

is used to determine the dynamic power dissipation (PD in µW):

PD

PD=CPD× V
fi= input frequency in MHz
fo= output frequency in MHz
∑ (CL× V
CL= output load capacitance in pF
VCC= supply voltage in V

2. For HC the condition is VI= GND to V
For HCT the condition is VI= GND to VCC− 1.5 V

=25°C; tr=tf= 6 ns

amb

propagation delay CP to Q

n

CL= 15 pF; VCC=5 V2224ns
maximum clock frequency 28 30 MHz
input capacitance 3.5 3.5 pF
power dissipation capacitance per flip-flop notes 1 and 2 36 38 pF

2

× fi+ ∑ (CL× V

CC

2

× fo) = sum of outputs

CC

2

× fo) where:

CC

CC

74HC/HCT190

TYPICAL

UNIT

HC HCT

ORDERING INFORMATION

“74HC/HCT/HCU/HCMOS Logic Package Information”

See

.

December 1990 3

Philips Semiconductors Product specification

Presettable synchronous BCD decade
up/down counter

PIN DESCRIPTION

PIN NO. SYMBOL NAME AND FUNCTION

3, 2, 6, 7 Q
4
5
8 GND ground (0 V)
11
12 TC terminal count output
13
14 CP clock input (LOW-to-HIGH, edge-triggered)
15, 1, 10, 9 D
16 V

to Q

0

3

CE count enable input (active LOW)
U/D up/down input

PL parallel load input (active LOW)

RC ripple clock output (active LOW)

to D

0

3

CC

flip-flop outputs

data inputs
positive supply voltage

74HC/HCT190

Fig.1 Pin configuration.

Fig.3 IEC logic symbol.

December 1990 4

Fig.2 Logic symbol.