Philips 74hc hct174 DATASHEETS
INTEGRATED CIRCUITS
DATA SH EET
For a complete data sheet, please also download:
•The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
•The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
•The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT174
Hex D-type flip-flop with reset;
positive-edge trigger
Product specification
Supersedes data of September 1993
File under Integrated Circuits, IC06
1998 Jul 08
Philips Semiconductors Product specification
Hex D-type flip-flop with reset; positive-edge trigger 74HC/HCT174
FEATURES
• Six edge-triggered D-type flip-flops
• Asynchronous master reset
• Output capability: standard
• ICC category: MSI
The 74HC/HCT174 have six edge-triggered D-type
flip-flops with individual D inputs and Q outputs. The
common clock (CP) and master reset (
reset (clear) all flip-flops simultaneously.
The register is fully edge-triggered. The state of each D
input, one set-up time prior to the LOW-to-HIGH clock
transition, is transferred to the corresponding output of the
GENERAL DESCRIPTION
The 74HC/HCT174 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
flip-flop.
A LOW level on the MR input forces all outputs LOW,
independently of clock or data inputs.
The device is useful for applications requiring true outputs
only and clock and master reset inputs that are common to
all storage elements.
QUICK REFERENCE DATA
GND = 0 V; T
=25°C; tr=tf= 6 ns
amb
SYMBOL PARAMETER CONDITIONS
t
PHL
f
max
C
C
I
PD
/ t
PLH
propagation delay CL= 15 pF; VCC=5 V
CP to Q
MR to Q
n
n
maximum clock frequency 99 69 MHz
input capacitance 3.5 3.5 pF
power dissipation
capacitance per flip-flop
notes 1 and 2 17 17 pF
MR) inputs load and
TYPICAL
UNIT
HC HCT
17 18 ns
13 17 ns
Notes
1. C
is used to determine the dynamic power dissipation (PD in µW):
PD
PD=CPD× V
2
× fi+∑ (CL× V
CC
2
× fo) where:
CC
fi= input frequency in MHz
fo= output frequency in MHz
∑ (CL× V
2
× fo) = sum of outputs
CC
CL= output load capacitance in pF
VCC= supply voltage in V
2. For HC the condition is VI= GND to V
CC
For HCT the condition is VI= GND to VCC− 1.5 V
1998 Jul 08 2
Philips Semiconductors Product specification
Hex D-type flip-flop with reset; positive-edge trigger 74HC/HCT174
ORDERING INFORMATION
TYPE
NUMBER
74HC174N;
NAME DESCRIPTION VERSION
DIP16 plastic dual in-line package; 16 leads (300 mil); long body SOT38-1
PACKAGE
74HCT174N
74HC174D;
SO16 plastic small outline package; 16 leads; body width 3.9 mm SOT109-1
74HCT174D
74HC174DB;
SSOP16 plastic shrink small outline package; 16 leads; body width 5.3 mm SOT338-1
74HCT174DB
74HC174PW;
TSSOP16 plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1
74HCT174PW
PIN DESCRIPTION
PIN NO. SYMBOL NAME AND FUNCTION
1
2, 5, 7, 10, 12, 15 Q
3, 4, 6, 11, 13, 14 D
MR asynchronous master reset (active LOW)
to Q
0
to D
0
5
5
flip-flop outputs
data inputs
8 GND ground (0 V)
9 CP clock input (LOW-to-HIGH, edge-triggered)
16 V
CC
positive supply voltage
Fig.1 Pin configuration. Fig.2 Fig.3 IEC logic symbol.
1998 Jul 08 3
Philips Semiconductors Product specification
Hex D-type flip-flop with reset; positive-edge trigger 74HC/HCT174
Fig.4 Functional diagram.
FUNCTION TABLE
OPERATING MODES
MR CP D
reset (clear) L X X L
load “1” H ↑ hH
load “0” H ↑ IL
Note
1. H = HIGH voltage level
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH CP transition
L = LOW voltage level
I = LOW voltage level one set-up time prior to the LOW-to-HIGH CP transition
X = don’t care
↑= LOW-to-HIGH CP transition
INPUTS OUTPUTS
n
Q
n
Fig.5 Logic diagram.
1998 Jul 08 4
Loading...