Philips 74hc hct163 DATASHEETS

INTEGRATED CIRCUITS

DATA SH EET

For a complete data sheet, please also download:

•The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications

•The IC06 74HC/HCT/HCU/HCMOS Logic Package Information

•The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines

74HC/HCT163

Presettable synchronous 4-bit
binary counter; synchronous reset

Product specification
File under Integrated Circuits, IC06

December 1990

Philips Semiconductors Product specification

Presettable synchronous 4-bit binary
counter; synchronous reset

FEATURES

• Synchronous counting and loading

• Two count enable inputs for n-bit cascading

• Positive-edge triggered clock

• Synchronous reset

• Output capability: standard

• ICC category: MSI

GENERAL DESCRIPTION

The 74HC/HCT163 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.

The 74HC/HCT163 are synchronous presettable binary
counters which feature an internal look-ahead carry and
can be used for high-speed counting.
Synchronous operation is provided by having all flip-flops
clocked simultaneously on the positive-going edge of the
clock (CP).
The outputs (Q
HIGH or LOW level. A LOW level at the parallel enable
input (PE) disables the counting action and causes the
data at the data inputs (D0 to D3) to be loaded into the
counter on the positive-going edge of the clock (providing
that the set-up and hold time requirements forPE are met).

to Q3) of the counters may be preset to a

0

74HC/HCT163

Preset takes place regardless of the levels at count enable
inputs (CEP and CET).

For the “163” the clear function is synchronous.
A LOW level at the master reset input (MR) sets all four

outputs of the flip-flops (Q0 to Q3) to LOW level after the
next positive-going transition on the clock (CP) input
(provided that the set-up and hold time requirements for
MR are met). This action occurs regardless of the levels at
PE, CET and CEP inputs.

This synchronous reset feature enables the designer to
modify the maximum count with only one external NAND
gate.

The look-ahead carry simplifies serial cascading of the
counters. Both count enable inputs (CEP and CET) must
be HIGH to count. The CET input is fed forward to enable
the terminal count output (TC). The TC output thus
enabled will produce a HIGH output pulse of a duration
approximately equal to a HIGH level output of Q0. This
pulse can be used to enable the next cascaded stage.

The maximum clock frequency for the cascaded counters
is determined by the CP to TC propagation delay and CEP
to CP set-up time, according to the following formula:

=

-------------------------------------------------------------------------------------------------

f

max

t

(CPtoTC) tSU(CEP to CP)+

P max()

1

QUICK REFERENCE DATA

GND = 0 V; T

=25°C; tr=tf=6ns

amb

SYMBOL PARAMETER CONDITIONS

HC HCT

t

PHL

f

max

C
C

/ t

I
PD

propagation delay

PLH

CP to Q
CP to TC
CET to TC

n

CL=15pF;
VCC=5V 17

21

11
maximum clock frequency 51 50 MHz
input capacitance 3.5 3.5 pF
power dissipation

notes 1 and 2 33 35 pF

capacitance per package

December 1990 2

TYPICAL

20
25
14

UNIT

ns
ns
ns

Notes

1. CPD is used to determine the
dynamic power dissipation
(PD in µW):

PD=CPD× V

∑ (CL× V

CC

CC

2

× fi+

2

× fo)
where:
fi= input frequency in MHz
fo= output frequency in MHz
∑ (CL× V

2

× fo) = sum of

CC

outputs
CL= output load capacitance in
pF
VCC= supply voltage in V

2. For HC the condition is
VI= GND to V

CC

For HCT the condition is

VI= GND to VCC− 1.5 V

Philips Semiconductors Product specification

Presettable synchronous 4-bit binary

74HC/HCT163

counter; synchronous reset

ORDERING INFORMATION

See

“74HC/HCT/HCU/HCMOS Logic Package Information”

PIN DESCRIPTION

PIN NO. SYMBOL NAME AND FUNCTION

1
2 CP clock input (LOW-to-HIGH, edge-triggered)
3, 4, 5, 6 D
7 CEP count enable input
8 GND ground (0 V)
9
10 CET count enable carry input
14, 13, 12, 11 Q
15 TC terminal count output
16 V

MR synchronous master reset (active LOW)

to D

0

3

PE parallel enable input (active LOW)

to Q

0

3

CC

.

data inputs

flip-flop outputs

positive supply voltage

Fig.1 Pin configuration.

December 1990 3

Fig.2 Logic symbol.

Fig.3 IEC logic symbol.

Philips Semiconductors Product specification

Presettable synchronous 4-bit binary
counter; synchronous reset

74HC/HCT163

Fig.4 Functional diagram.

FUNCTION TABLE

INPUTS OUTPUTS

OPERATING MODE

MR CP CEP CET PE D

n

Q

n

TC

reset (clear) I ↑ XXXXL L
parallel load h

h
count h ↑ h h h X count
hold

(do nothing)

h

h

↑
↑

X
X

X
X

I
X

X
X

X
I

I
I

h
h

I
h

X
X

L
H

q

n

q

n

L

(1)
(1)
(1)

L

Notes

1. The TC output is HIGH when CET is HIGH and the counter is at terminal count (HHHH).
H = HIGH voltage level
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH CP transition
L = LOW voltage level
I = LOW voltage level one set-up time prior to the LOW-to-HIGH CP transition
q = lower case letters indicate the state of the referenced output one set-up time prior to the

LOW-to-HIGH CP transition
X = don’t care
↑ = LOW-to-HIGH CP transition

December 1990 4