Philips 74hc hct161 DATASHEETS

INTEGRATED CIRCUITS

DATA SH EET

For a complete data sheet, please also download:

•The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications

•The IC06 74HC/HCT/HCU/HCMOS Logic Package Information

•The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines

74HC/HCT161

Presettable synchronous 4-bit binary counter; asynchronous reset

Product speciﬁcation File under Integrated Circuits, IC06

December 1990

Philips Semiconductors Product speciﬁcation

Presettable synchronous 4-bit binary counter; asynchronous reset

FEATURES

• Synchronous counting and loading

• Two count enable inputs for n-bit cascading

• Positive-edge triggered clock

• Asynchronous reset

• Output capability: standard

• ICC category: MSI

GENERAL DESCRIPTION

The 74HC/HCT161 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A.

The 74HC/HCT161 are synchronous presettable binary counters which feature an internal look-ahead carry and can be used for high-speed counting. Synchronous operation is provided by having all flip-flops clocked simultaneously on the positive-going edge of the clock (CP). The outputs (Q HIGH or LOW level. A LOW level at the parallel enable

to Q3) of the counters may be preset to a

74HC/HCT161

input (PE) disables the counting action and causes the data at the data inputs (D0 to D3) to be loaded into the counter on the positive-going edge of the clock (providing that the set-up and hold time requirements forPE are met). Preset takes place regardless of the levels at count enable inputs (CEP and CET).

A LOW level at the master reset input (MR) sets all four outputs of the flip-flops (Q0 to Q3) to LOW level regardless of the levels at CP, PE, CET and CEP inputs (thus providing an asynchronous clear function).

The look-ahead carry simplifies serial cascading of the counters. Both count enable inputs (CEP and CET) must be HIGH to count. The CET input is fed forward to enable the terminal count output (TC). The TC output thus enabled will produce a HIGH output pulse of a duration approximately equal to a HIGH level output of Q0. This pulse can be used to enable the next cascaded stage.

The maximum clock frequency for the cascaded counters is determined by the CP to TC propagation delay and CEP to CP set-up time, according to the following formula:

max

---------------------------------------------------------------------------------------------------

(CP to TC) t+SU(CEP to CP)

P(max)

QUICK REFERENCE DATA

GND = 0 V; T

=25°C; tr=tf= 6 ns

amb

SYMBOL PARAMETER CONDITIONS

PHL

/ t

propagation delay

PLH

CP to Q

CL= 15 pF;

VCC=5 V 19 CP to TC MR to Q

MR to TC CET to TC

max

C C

I PD

maximum clock frequency 44 45 MHz input capacitance 3.5 3.5 pF power dissipation

notes 1 and 2 33 35 pF

capacitance per package

TYPICAL

HC HCT

20 21 20 20 10

UNIT

ns ns ns ns ns

Notes

1. CPD is used to determine the dynamic power dissipation (PD in µW):

× fi+

× fo)

PD=CPD× V

∑ (CL× V

where: fi= input frequency in MHz fo= output frequency in MHz ∑ (CL× V

× fo) = sum of

outputs CL= output load capacitance in

pF VCC= supply voltage in V

2. For HC the condition is VI= GND to V

For HCT the condition is

VI= GND to VCC− 1.5 V

December 1990 2

Philips Semiconductors Product speciﬁcation

Presettable synchronous 4-bit binary counter; asynchronous reset

ORDERING INFORMATION

See

“74HC/HCT/HCU/HCMOS Logic Package Information”

PIN DESCRIPTION

PIN NO. SYMBOL NAME AND FUNCTION

1 2 CP clock input (LOW-to-HIGH, edge-triggered) 3, 4, 5, 6 D 7 CEP count enable input 8 GND ground (0 V) 9 10 CET count enable carry input 14, 13, 12, 11 Q 15 TC terminal count output 16 V

MR asynchronous master reset (active LOW)

to D

PE parallel enable input (active LOW)

to Q

data inputs

ﬂip-ﬂop outputs

positive supply voltage

74HC/HCT161

Fig.1 Pin configuration. Fig.2 Logic symbol. Fig.3 IEC logic symbol.

December 1990 3

Philips Semiconductors Product speciﬁcation

Presettable synchronous 4-bit binary counter; asynchronous reset

Fig.4 Functional diagram.

74HC/HCT161

FUNCTION TABLE

INPUTS OUTPUTS

OPERATING MODE

MR CP CEP CET PE D

reset (clear) L X X X X X L L parallel load H

↑ ↑

X X

I I

I h

H count H ↑ h h h X count hold

(do nothing)

H H

X X

I X

X I

h h

X X

Note

1. The TC output is HIGH when CET is HIGH and the counter is at terminal count (HHHH). H = HIGH voltage level h = HIGH voltage level one set-up time prior to the LOW-to-HIGH CP transition L = LOW voltage level I = LOW voltage level one set-up time prior to the LOW-to-HIGH CP transition q = lower case letters indicate the state of the referenced output one set-up time prior to the

LOW-to-HIGH CP transition X = don’t care ↑ = LOW-to-HIGH CP transition

(1) (1) (1)

December 1990 4

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