Philips 74hc hct160 DATASHEETS
INTEGRATED CIRCUITS
DATA SH EET
For a complete data sheet, please also download:
•The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
•The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
•The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT160
Presettable synchronous BCD
decade counter; asynchronous
reset
Product specification
File under Integrated Circuits, IC06
December 1990
Philips Semiconductors Product specification
Presettable synchronous BCD decade
counter; asynchronous reset
FEATURES
• Synchronous counting and loading
• Two count enable inputs for n-bit cascading
• Positive-edge triggered clock
• Asynchronous reset
• Output capability: standard
• ICC category: MSI
GENERAL DESCRIPTION
The 74HC/HCT160 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT160 are synchronous presettable decade
counters which feature an internal look-ahead carry and
can be used for high-speed counting.
Synchronous operation is provided by having all flip-flops
clocked simultaneously on the positive-going edge of the
clock (CP).
The outputs (Q
HIGH or LOW level. A LOW level at the parallel enable
to Q3) of the counters may be preset to a
0
74HC/HCT160
input (PE) disables the counting action and causes the
data at the data inputs (D0 to D3) to be loaded into the
counter on the positive-going edge of the clock (providing
that the set-up and hold time requirements forPE are met).
Preset takes place regardless of the levels at count enable
inputs (CEP and CET).
A LOW level at the master reset input (MR) sets all four
outputs of the flip-flops (Q0 to Q3) to LOW level regardless
of the levels at CP, PE, CET and CEP inputs (thus
providing an asynchronous clear function).
The look-ahead carry simplifies serial cascading of the
counters. Both count enable inputs (CEP and CET) must
be HIGH to count. The CET input is fed forward to enable
the terminal count output (TC). The TC output thus
enabled will produce a HIGH output pulse of a duration
approximately equal to a HIGH level output of Q0. This
pulse can be used to enable the next cascaded stage.
The maximum clock frequency for the cascaded counters
is determined by the CP to TC propagation delay and CEP
to CP set-up time, according to the following formula:
f
max
---------------------------------------------------------------------------------------------------------
=
t
P max()
CP to TC()+tSU(CEP to CP)
1
QUICK REFERENCE DATA
GND = 0 V; T
=25°C; tr=tf= 6 ns
amb
SYMBOL PARAMETER CONDITIONS
t
PHL
propagation delay
CP to Q
n
CL=15pF;
VCC=5V 19
CP to TC
MR to Q
n
MR to TC
CET to TC
t
PLH
propagation delay
CP to Q
n
CP to TC
CET to TC
f
max
maximum clock
frequency
C
I
C
PD
input capacitance 3.5 3.5 pF
power dissipation
notes 1 and 2
capacitance per
package
TYPICAL
UNIT
HC HCT
21
21
21
14
19
21
14
21
24
23
26
14
21
20
7
ns
ns
ns
ns
ns
ns
ns
ns
61 31 MHz
39 34 pF
Notes
1. CPD is used to determine the
dynamic power dissipation
(PD in µW):
PD=CPD× V
∑ (CL× V
CC
2
CC
× fi+
2
× fo)
where:
fi= input frequency in MHz
fo= output frequency in MHz
∑ (CL× V
2
× fo) = sum of
CC
outputs
CL= output load capacitance in
pF
VCC= supply voltage in V
2. For HC the condition is
VI= GND to V
CC
For HCT the condition is
VI= GND to VCC− 1.5 V
December 1990 2
Philips Semiconductors Product specification
Presettable synchronous BCD decade
counter; asynchronous reset
ORDERING INFORMATION
See
“74HC/HCT/HCU/HCMOS Logic Package Information”
PIN DESCRIPTION
PIN NO. SYMBOL NAME AND FUNCTION
1
2 CP clock input (LOW-to-HIGH, edge-triggered)
3, 4, 5, 6 D
7 CEP count enable input
8 GND ground (0 V)
9
10 CET count enable carry input
14, 13, 12, 11 Q
15 TC terminal count output
16 V
MR asynchronous master reset (active LOW)
to D
0
3
PE parallel enable input (active LOW)
to Q
0
3
CC
data inputs
flip-flop outputs
positive supply voltage
.
74HC/HCT160
Fig.1 Pin configuration. Fig.2 Logic symbol. Fig.3 IEC logic symbol.
December 1990 3
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