Philips 74hc hct139 DATASHEETS

INTEGRATED CIRCUITS

DATA SH EET

For a complete data sheet, please also download:

•The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications

•The IC06 74HC/HCT/HCU/HCMOS Logic Package Information

•The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines

74HC/HCT139

Dual 2-to-4 line decoder/demultiplexer

Product speciﬁcation File under Integrated Circuits, IC06

September 1993

Philips Semiconductors Product speciﬁcation

Dual 2-to-4 line decoder/demultiplexer 74HC/HCT139

FEATURES

• Demultiplexing capability

• Two independent 2-to-4 decoders

• Multifunction capability

• Active LOW mutually exclusive outputs

• Output capability: standard

• ICCcategory: MSI

GENERAL DESCRIPTION

The 74HC/HCT139 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard no. 7A.

The 74HC/HCT139 are high-speed, dual 2-to-4 line decoder/multiplexers. This device has two independent decoders, each accepting two binary weighted inputs (nA0and nA1) and providing four mutually exclusive active LOW outputs (nY0 to nY3). Each decoder has an active LOW enable input (nE). When nE is HIGH, every output is forced HIGH. The enable can be used as the data input for a 1-to-4 demultiplexer application. The “139” is identical to the HEF4556 of the HE4000B family.

QUICK REFERENCE DATA

GND = 0 V; T

= 25 °C; tr= tf= 6 ns

amb

SYMBOL PARAMETER CONDITIONS

PHL

C C

I PD

/ t

PLH

propagation delay CL= 15 pF; VCC= 5 V

to nY

E3to nY

input capacitance 3.5 3.5 pF power dissipation capacitance per multiplexer notes 1 and 2 42 44 pF

TYPICAL

UNIT

HC HCT

11 13 ns 10 13 ns

Notes

1. C

is used to determine the dynamic power dissipation (PDin µW):

PD= CPD× V

× fi+∑(CL× V

× fo) where:

fi= input frequency in MHz fo= output frequency in MHz ∑ (CL× V

× fo) = sum of outputs

CL= output load capacitance in pF VCC= supply voltage in V

2. For HC the condition is VI= GND to V

For HCT the condition is VI= GND to VCC− 1.5 V

APPLICATIONS

• Memory decoding or data-routing

• Code conversion

ORDERING INFORMATION

See

“74HC/HCT/HCU/HCMOS Logic Package Information”

September 1993 2

Philips Semiconductors Product speciﬁcation

Dual 2-to-4 line decoder/demultiplexer 74HC/HCT139

PIN DESCRIPTION

PIN NO. SYMBOL NAME AND FUNCTION

1, 15 1 2, 3 1A 4, 5, 6, 7 1 8 GND ground (0 V) 12, 11, 10, 9 2 14, 13 2A 16 V

E, 2E enable inputs (active LOW)

, 1A

Y0to 1Y

Y0to 2Y

, 2A

address inputs outputs (active LOW)

outputs (active LOW) address inputs positive supply voltage

Fig.1 Pin configuration.

(a) (b)

Fig.2 Logic symbol.

Fig.3 IEC logic symbol.

September 1993 3

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