Philips 74hc hct138 DATASHEETS

INTEGRATED CIRCUITS

DATA SH EET

For a complete data sheet, please also download:

•The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications

•The IC06 74HC/HCT/HCU/HCMOS Logic Package Information

•The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines

74HC/HCT138

3-to-8 line decoder/demultiplexer;
inverting

Product specification
File under Integrated Circuits, IC06

September 1993

Philips Semiconductors Product specification

3-to-8 line decoder/demultiplexer; inverting 74HC/HCT138

FEATURES

• Demultiplexing capability

• Multiple input enable for easy expansion

• Ideal for memory chip select decoding

• Active LOW mutually exclusive outputs

• Output capability: standard

• ICCcategory: MSI

The 74HC/HCT138 decoders accept three binary
weighted address inputs (A
provide 8 mutually exclusive active LOW outputs (Y0to
Y7).

The “138” features three enable inputs: two active LOW
(E1and E2) and one active HIGH (E3). Every output will be
HIGH unless E1and E2are LOW and E3is HIGH.

This multiple enable function allows easy parallel
expansion of the “138” to a 1-of-32 (5 lines to 32 lines)
decoder with just four “138” ICs and one inverter.

GENERAL DESCRIPTION

The 74HC/HCT138 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.

The ”138” can be used as an eight output demultiplexer by
using one of the active LOW enable inputs as the data
input and the remaining enable inputs as strobes. Unused
enable inputs must be permanently tied to their
appropriate active HIGH or LOW state.

The ”138” is identical to the “238” but has inverting outputs.

QUICK REFERENCE DATA

GND = 0 V; T

= 25 °C; tr= tf= 6 ns

amb

SYMBOL PARAMETER CONDITIONS

= 15 pF; VCC= 5 V

L

t

PHL

t

PHL

C
C

I
PD

propagation delay C

/ t

PLH

/ t

PLH

Anto Y
E3to Y

Ento Y

n
n

n

input capacitance 3.5 3.5 pF
power dissipation capacitance per package notes 1 and 2 67 67 pF

, A1, A2) and when enabled,

0

TYPICAL

HC HCT

12 17 ns
14 19 ns

UNIT

Notes

1. C

is used to determine the dynamic power dissipation (PDin µW):

PD

PD= CPD× V

2

× fi+∑(CL× V

CC

2

× fo) where:

CC

fi= input frequency in MHz
fo= output frequency in MHz
∑ (CL× V

2

× fo) = sum of outputs

CC

CL= output load capacitance in pF
VCC= supply voltage in V

2. For HC the condition is VI= GND to V

CC

For HCT the condition is VI= GND to VCC− 1.5 V

ORDERING INFORMATION

See

“74HC/HCT/HCU/HCMOS Logic Package Information”

September 1993 2

.

Philips Semiconductors Product specification

3-to-8 line decoder/demultiplexer; inverting 74HC/HCT138

PIN DESCRIPTION

PIN NO. SYMBOL NAME AND FUNCTION

1, 2, 3 A
4, 5
6E
8 GND ground (0 V)
15, 14, 13, 12, 11, 10, 9, 7
16 V

to A

0

2

E1, E

2

3

Y0 to Y

7

CC

address inputs
enable inputs (active LOW)
enable input (active HIGH)

outputs (active LOW)
positive supply voltage

handbook, halfpage

1
2
3

4
5
6

A

0

A

1

A

2

E

1

E

2

E

3

Y
Y
Y
Y
Y
Y
Y
Y

MLB312

0
1
2
3
4
5
6
7

Fig.1 Pin configuration. Fig.2 Logic symbol.

15
14
13
12
11
10
9
7

(a) (b)

Fig.3 IEC logic symbol.

September 1993 3

Fig.4 Functional diagram.