Philips 74hc hct109 DATASHEETS
INTEGRATED CIRCUITS
DATA SH EET
For a complete data sheet, please also download:
•The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
•The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
•The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT109
Dual J
K flip-flop with set and reset;
positive-edge trigger
Product specification
Supersedes data of December 1990
File under Integrated Circuits, IC06
1997 Nov 25
Philips Semiconductors Product specification
Dual JK flip-flop with set and reset;
positive-edge trigger
(
FEATURES
• J, K inputs for easy D-type flip-flop
• Toggle flip-flop or “do nothing” mode
• Output capability: standard
• ICCcategory: flip-flops
GENERAL DESCRIPTION
The 74HC/HCT109 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT109 are dual positive-edge triggered, J
K
flip-flops with individual J, K inputs, clock (CP) inputs, set
QUICK REFERENCE DATA
GND = 0 V; T
= 25 °C; tr= tf= 6 ns
amb
SYMBOL PARAMETER CONDITIONS
t
/ t
PHL
PLH
f
max
C
I
C
PD
propagation delay
nCP to nQ, n
n
S
to nQ, nQ1214ns
D
n
R
to nQ, nQ1215ns
D
Q1517ns
CL= 15 pF;
VCC= 5 V
maximum clock frequency 75 61 MHz
input capacitance 3.5 3.5 pF
power dissipation
capacitance per flip-flop
notes 1 and 2
SD) and reset (RD) inputs; also complementary Q and Q
outputs.
The set and reset are asynchronous active LOW inputs
and operate independently of the clock input.
The J and K inputs control the state changes of the
flip-flops as described in the mode select function table.
The J and Kinputs must be stable one set-up time prior to
the LOW-to-HIGH clock transition for predictable
operation.
The JK design allows operation as a D-type flip-flop by
tying the J and K inputs together.
Schmitt-trigger action in the clock input makes the circuit
highly tolerant to slower clock rise and fall times.
74HC/HCT109
TYPICAL
UNIT
HC HCT
20 22 pF
Notes
1. C
is used to determine the dynamic power dissipation (PDin µW):
PD
PD= CPD× V
2
× fi+∑(CL× V
CC
2
× fo) where:
CC
fi= input frequency in MHz
fo= output frequency in MHz
∑ (CL× V
2
× fo) = sum of outputs
CC
CL= output load capacitance in pF
VCC= supply voltage in V
2. For HC the condition is VI= GND to V
CC
For HCT the condition is VI= GND to VCC− 1.5 V.
ORDERING INFORMATION
See
“74HC/HCT/HCU/HCMOS Logic Package Information”
1997 Nov 25 2
.
Philips Semiconductors Product specification
Dual JK flip-flop with set and reset;
74HC/HCT109
positive-edge trigger
PIN DESCRIPTION
PIN NO. SYMBOL NAME AND FUNCTION
1, 15 1
2, 14, 3, 13 1J, 2J, 1
4, 12 1CP, 2CP clock input (LOW-to-HIGH, edge-triggered)
5, 11 1
6, 10 1Q, 2Q true flip-flop outputs
7, 9 1
8 GND ground (0 V)
16 V
RD, 2R
D
K, 2K synchronous inputs; flip-flops 1 and 2
SD, 2S
D
Q, 2Q complement flip-flop outputs
CC
asynchronous reset-direct input (active LOW)
asynchronous set-direct input (active LOW)
positive supply voltage
Fig.1 Pin configuration. Fig.2 Logic symbol. Fig.3 IEC logic symbol.
1997 Nov 25 3
Loading...