Philips 74hc hct107 DATASHEETS
INTEGRATED CIRCUITS
DATA SH EET
For a complete data sheet, please also download:
•The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
•The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
•The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT107
Dual JK flip-flop with reset;
negative-edge trigger
Product specification
File under Integrated Circuits, IC06
December 1990
Philips Semiconductors Product specification
Dual JK flip-flop with reset; negative-edge trigger 74HC/HCT107
FEATURES
• Output capability: standard
• ICC category: flip-flops
The 74HC/HCT107 are dual negative-edge triggered
JK-type flip-flops featuring individual J, K, clock (n
reset (nR) inputs; also complementary Q and Q outputs.
The J and K inputs must be stable one set-up time prior to
the HIGH-to-LOW clock transition for predictable
GENERAL DESCRIPTION
The 74HC/HCT107 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
operation.
The reset (nR) is an asynchronous active LOW input.
When LOW, it overrides the clock and data inputs, forcing
the Q output LOW and the Q output HIGH.
Schmitt-trigger action in the clock input makes the circuit
highly tolerant to slower clock rise and fall times.
QUICK REFERENCE DATA
GND = 0 V; T
= 25 °C; tr= tf= 6 ns
amb
SYMBOL PARAMETER CONDITIONS
/ t
t
PHL
PLH
f
max
C
I
C
PD
propagation delay
n
CP to nQ 16 16 ns
n
CP to nQ 1618ns
n
R to nQ, nQ 1617ns
CL= 15 pF;
VCC= 5 V
maximum clock frequency 78 73 MHz
input capacitance 3.5 3.5 pF
power dissipation
capacitance per flip-flop
notes 1 and 2 30 30 pF
CP) and
TYPICAL
UNIT
HC HCT
Notes
1. C
is used to determine the dynamic power dissipation (PDin µW):
PD
PD= CPD× V
2
× fi+∑(CL× V
CC
2
× fo) where:
CC
fi= input frequency in MHz
fo= output frequency in MHz
∑ (CL× V
2
× fo) = sum of outputs
CC
CL= output load capacitance in pF
VCC= supply voltage in V
2. For HC the condition is VI= GND to V
CC
For HCT the condition is VI= GND to VCC− 1.5 V.
ORDERING INFORMATION
“74HC/HCT/HCU/HCMOS Logic Package Information”
See
December 1990 2
.
Philips Semiconductors Product specification
Dual JK flip-flop with reset; negative-edge trigger 74HC/HCT107
PIN DESCRIPTION
PIN NO. SYMBOL NAME AND FUNCTION
1, 8, 4, 11 1J, 2J, 1K, 2K synchronous inputs; flip-flops 1 and 2
2, 6 1
3, 5 1Q, 2Q true flip-flop outputs
7 GND ground (0 V)
12, 9 1
13, 10 1
14 V
Q, 2Q complement flip-flop outputs
CP, 2CP clock input (HIGH-to-LOW, edge-triggered)
R, 2R asynchronous reset inputs (active LOW)
CC
positive supply voltage
Fig.1 Pin configuration. Fig.2 Logic symbol. Fig.3 IEC logic symbol.
December 1990 3
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