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DATA SH EET
Product specification
File under Integrated Circuits, IC06
December 1990
INTEGRATED CIRCUITS
74HC/HCT00
Quad 2-input NAND gate
For a complete data sheet, please also download:
•The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
•The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
•The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
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December 1990 2
Philips Semiconductors Product specification
Quad 2-input NAND gate 74HC/HCT00
FEATURES
• Output capability: standard
• ICC category: SSI
GENERAL DESCRIPTION
The 74HC/HCT00 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL).
They are specified in compliance with JEDEC standard no. 7A.
The 74HC/HCT00 provide the 2-input NAND function.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25 °C; tr= tf= 6 ns
Notes
1. C
PD
is used to determine the dynamic power dissipation (PDin µW):
PD= CPD× V
CC
2
× fi+ ∑ (CL× V
CC
2
× fo) where:
fi= input frequency in MHz
fo= output frequency in MHz
CL= output load capacitance in pF
VCC= supply voltage in V
Σ (CL× V
CC
2
× fo) = sum of outputs
2. For HC the condition is VI= GND to V
CC
For HCT the condition is VI= GND to VCC− 1.5 V
ORDERING INFORMATION
See
“74HC/HCT/HCU/HCMOS Logic Package Information”
.
SYMBOL PARAMETER CONDITIONS
TYPICAL
UNIT
HC HCT
t
PHL
/ t
PLH
propagation delay nA, nB to nY CL= 15 pF; VCC=5V 7 10 ns
C
I
input capacitance 3.5 3.5 pF
C
PD
power dissipation capacitance per gate notes 1 and 2 22 22 pF