Philips 74HC58DB, 74HC58D, 74HC58U, 74HC58N Datasheet
DATA SH EET
Product specification
File under Integrated Circuits, IC06
December 1990
INTEGRATED CIRCUITS
74HC58
Dual AND-OR gate
For a complete data sheet, please also download:
•The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
•The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
•The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
December 1990 2
Philips Semiconductors Product specification
Dual AND-OR gate 74HC58
FEATURES
• Output capability: standard
• ICC category: SSI
GENERAL DESCRIPTION
The 74HC58 is a high-speed Si-gate CMOS device and is pin compatible with low power Schottky TTL (LSTTL).
It is specified in compliance with JEDEC standard no. 7A.
The “58” provides two sections of AND-OR gates. One section contains a 2-wide, 3-input (1A to 1F) AND-OR gate and
the second section contains a 2-wide, 2-input (2A to 2D) AND-OR gate.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 15 °C; tr= tf= 6 ns
Notes
1. C
PD
is used to determine the dynamic power dissipation (PDin µW):
PD= CPD× V
CC
2
× fi+ ∑ (CL× V
CC
2
× fo) where:
fi= input frequency in MHz
fo= output frequency in MHz
CL= output load capacitance in pF
VCC= supply voltage in V
∑ (CL× V
CC
2
× fo) = sum of outputs
2. For HC the condition is VI= GND to V
CC
ORDERING INFORMATION
See
“74HC/HCT/HCU/HCMOS Logic Package Information”
.
SYMBOL PARAMETER CONDITIONS
TYPICAL
UNIT
HC
t
PHL
/ t
PLH
propagation delay CL= 15 pF; VCC= 5 V
1n to 1Y 11 ns
2n to 2Y 9 ns
C
I
input capacitance 3.5 pF
C
PD
power dissipation capacitance per
gate
notes 1 and 2 18 pF
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