Philips 74HCT563U, 74HCT563N, 74HCT563DB, 74HCT563D, 74HC563N Datasheet

DATA SH EET

Product specification
File under Integrated Circuits, IC06

December 1990

INTEGRATED CIRCUITS

74HC/HCT563

Octal D-type transparent latch;
3-state; inverting

For a complete data sheet, please also download:

•The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications

•The IC06 74HC/HCT/HCU/HCMOS Logic Package Information

•The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines

December 1990 2

Philips Semiconductors Product specification

Octal D-type transparent latch; 3-state;
inverting

74HC/HCT563

FEATURES

• 3-state inverting outputs for bus
oriented applications

• Inputs and outputs on opposite
sides of package allowing easy
interface with microprocessor

• Common 3-state output enable
input

• Output capability: bus driver

• ICC category: MSI

GENERAL DESCRIPTION

The 74HC/HCT563 are high-speed
Si-gate CMOS devices and are pin
compatible with low power Schottky

TTL (LSTTL). They are specified in
compliance with JEDEC standard no.
7A.

The 74HC/HCT563 are octal D-type
transparent latches featuring
separate D-type inputs for each latch
and inverting 3-state outputs for bus
oriented applications.
A latch enable (LE) input and an
output enable (

OE) input are common

to all latches.
The “563” is functionally identical to

the “573”, but has inverted outputs.
The “563” consists of eight D-type

transparent latches with 3-state
inverting outputs. The LE and OE are

common to all latches.
When LE is HIGH, data at the D

n

inputs enter the latches. In this
condition the latches are transparent,
i.e. a latch output will change state
each time its corresponding D-input
changes.

When LE is LOW the latches store the
information that was present at the
D-inputs a set-up time preceding the
HIGH-to-LOW transition of LE.
When OE is LOW, the contents of the
8 latches are available at the outputs.
When OE is HIGH, the outputs go to
the high impedance OFF-state.
Operation of the OE input does not
affect the state of the latches.

QUICK REFERENCE DATA

GND = 0 V; T

amb

=25°C; tr=tf= 6 ns

Notes

1. C

PD

is used to determine the dynamic power dissipation (PD in µW):

PD=CPD× V

CC

2

× fi+ ∑ (CL× V

CC

2

× fo) where:
fi= input frequency in MHz
fo= output frequency in MHz
∑ (CL× V

CC

2

× fo) = sum of outputs
CL= output load capacitance in pF
VCC= supply voltage in V

2. For HC the condition is VI= GND to V

CC

for HCT the condition is VI= GND to VCC− 1.5 V

ORDERING INFORMATION

See

“74HC/HCT/HCU/HCMOS Logic Package Information”

.

SYMBOL PARAMETER CONDITIONS

TYPICAL

UNIT

HC HCT

t

PHL/ tPLH

propagation delay Dn, LE to Q

n

CL= 15 pF; VCC=5 V 14 16 ns

C

I

input capacitance 3.5 3.5 pF

C

PD

power dissipation capacitance per latch notes 1 and 2 19 19 pF

December 1990 3

Philips Semiconductors Product specification

Octal D-type transparent latch; 3-state;
inverting

74HC/HCT563

PIN DESCRIPTION

PIN NO. SYMBOL NAME AND FUNCTION

2, 3, 4, 5, 6, 7, 8, 9 D

0

to D

7

data inputs
11 LE latch enable input (active HIGH)
1

OE 3-state output enable input (active LOW)
10 GND ground (0 V)
19, 18, 17, 16, 15, 14, 13, 12

Q0 to Q

7

3-state latch outputs

20 V

CC

positive supply voltage

Fig.1 Pin configuration. Fig.2 Logic symbol. Fig.3 IEC logic symbol.