Philips 74HCT5555N, 74HCT5555D, 74HC5555D, 74HC5555U, 74HC5555N Datasheet

DATA SH EET

Product speciﬁcation File under Integrated Circuits, IC06

September 1993

INTEGRATED CIRCUITS

74HC/HCT5555

Programmable delay timer with oscillator

For a complete data sheet, please also download:

•The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications

•The IC06 74HC/HCT/HCU/HCMOS Logic Package Information

•The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines

September 1993 2

Philips Semiconductors Product speciﬁcation

Programmable delay timer with oscillator 74HC/HCT5555

FEATURES

• Positive and negative edge triggered

• Retriggerable or non-retriggerable

• Programmable delay

minimum: 100 ns maximum: depends on input

frequency and division ratio

• Divide-by range of 2 to 2

• Direct reset terminates output pulse

• Very low power consumption in triggered start mode

• 3 oscillator operating modes: – RC oscillator – Crystal oscillator – External oscillator

• Device is unaffected by variations in temperature and VCC when using an external oscillator

• Automatic power-ON reset

• Schmitt trigger action on both

trigger inputs

• Direct drive for a power transistor

• Low power consumption in active

mode with respect to TTL type timers

• High precision due to digital timing

• Output capability: 20 mA

• ICC category: MSI.

APPLICATIONS

• Motor control

• Attic fan timers

• Delay circuits

• Automotive applications

• Precision timing

• Domestic appliances.

GENERAL DESCRIPTION

The 74HC/HCT5555 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A.

The 74HC/HCT5555 are precision programmable delay timers which consist of:

• 24-stage binary counter

• integrated oscillator (using external

timing components)

• retriggerable/non-retriggerable monostable

• automatic power-ON reset

• output control logic

• oscillator control logic

• overriding asynchronous master

reset (MR).

QUICK REFERENCE DATA

GND = 0 V; T

amb

= 25 °C; tr = tf = 6 ns.

Notes

1. C

is used to determine the dynamic power dissipation (PD in µW):

PD = CPD x V

x fi + Σ(CL x V

x fo) where: fi = input frequency in MHz fo = output frequency in MHz Σ(CL x V

x fo) = sum of outputs. CL = output load capacitance in pF VCC = supply voltage in V

2. For HC the condition is VI = GND to V

For HCT the condition is VI= GND to VCC− 1.5 V.

ORDERING INFORMATION

SYMBOL PARAMETER CONDITIONS TYP. UNIT

PHL/tPLH

propagation delay CL = 15 pF;

VCC= 5 V

B to Q/Q2424ns

MR to Q/

Q1920ns

RS to Q/

Q2628ns

input capacitance 3.5 3.5 pF

power dissipation capacitance per buffer

notes 1 and 2 23 36 pF

EXTENDED TYPE

NUMBER

PACKAGE

PINS PIN POSITION MATERIAL CODE

74HC/HCT5555N 16 DIL plastic SOT38Z 74HC/HCT5555D 16 SO16 plastic SOT109A

September 1993 3

Philips Semiconductors Product speciﬁcation

Programmable delay timer with oscillator 74HC/HCT5555

PINNING

SYMBOL PIN DESCRIPTION

RS 1 clock input/oscillator pin R

2 external resistor connection

3 external capacitor connection

A 4 trigger input (positive-edge

triggered)

B 5 trigger input (negative-edge

triggered)

RTR/

RTR 6 retriggerable/non-retriggerable

input (active HIGH/active LOW) Q 7 pulse output (active LOW) GND 8 ground (0 V) Q 9 pulse output (active HIGH) S

− S

10, 11,

12, 13

programmable input

OSC CON 14 oscillator control MR 15 master reset input (active

HIGH) V

16 positive supply voltage

Fig.1 Pin configuration.

handbook, halfpage

1 2 3 4 5 6 7 8

16 15 14 13 12 11 10

5555

GND

MGA642

OSC CON

A B

RTR/

RTR

Fig.2 IEC logic diagram.

handbook, halfpage

MGA643

I = 0

CT = 0

CT = m R

V16

16G17

1 2 4 8

X / Y CTRDIVm

[T]

Y = 0

Y = 15

! G

10 11 12 13

2 3

1 6

4 5

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Philips Semiconductors Product speciﬁcation

Programmable delay timer with oscillator 74HC/HCT5555

Fig.3 Functional diagram.

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MGA644

MONOSTABLE

CIRCUITRY

OSC CON

MR A

5 6

9 7

2 3 10 11 12 13

POWER-ON

RESET

RTR/RTR

OUTPUT

STAGE

24 - STAGE COUNTER

012

SSSS

FUNCTIONAL DESCRIPTION

The oscillator configuration allows the design of RC or crystal oscillator circuits. The device can operate from an external clock signal applied to the RS input (RTC and CTC must not be connected). The oscillator frequency is determined by the external timing components (RT and CT), within the frequency range 1 Hz to 4 MHz (32 kHz to 20 MHz with crystal oscillator).

In the HCT version the MR input is TTL compatible but the RS input has CMOS input switching levels. The RS input can be driven by TTL input levels if RS is tied to VCC via a pull-up resistor.

The counter divides the frequency to obtain a long pulse duration. The 24-stage is digitally programmed via the select inputs (S0 to S3). Pin S3 can also be used to select the test mode, which is a convenient way of functionally testing the counter.

The “5555” is triggered on either the positive-edge, negative-edge or both.

• Trigger pulse applied to input A for positive-edge triggering

• Trigger pulse applied input

B for

negative-edge triggering

• Trigger pulse applied to inputs A and B (tied together) for both positive-edge and negative triggering.

The Schmitt trigger action in the trigger inputs, transforms slowly changing input signals into sharply defined jitter-free output signals and provides the circuit with excellent noise immunity.

The OSC CON input is used to select the oscillator mode, either continuously running (OSC CON = HIGH) or triggered start mode (OSC CON = LOW). The continuously running mode is selected where a start-up delay is an undesirable feature and the triggered start mode is selected where very low power consumption is the primary concern.

The start of the programmed time delay occurs when output Q goes HIGH (in the triggered start mode, the previously disabled oscillator will start-up). After the programmed time delay, the flip-flop stages are reset and the output returns to its original state.

An internal power-on reset is used to reset all flip-flop stages.

The output pulse can be terminated by the asynchronous overriding master reset (MR), this results in all flip-flop stages being reset. The output signal is capable of driving a power transistor. The output time delay is calculated using the following formula (minimum time delay is 100 ns):

Once triggered, the output width may be extended by retriggering the gated, active HIGH-going input A or the active LOW-going input

B. By repeating this process, the output pulse period (Q = HIGH, Q = LOW) can be made as long as desired. This mode is selected by RTR/RTR = HIGH. A LOW on RTR/RTR makes, once triggered, the outputs (Q, Q) independent of further transitions of inputs A and B.

1 f

-- -

division ratio (s).×

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Philips Semiconductors Product speciﬁcation

Programmable delay timer with oscillator 74HC/HCT5555

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MGA655

RTCC

OSC

CON

RTR/

RTR

Q CP

Fig.4 Logic diagram.

September 1993 6

Philips Semiconductors Product speciﬁcation

Programmable delay timer with oscillator 74HC/HCT5555

TEST MODE

Set S3 to a logic LOW level, this will divide the 24 stage counter into three, parallel clocking, 8-stage counters. Set S0, S1 and S2 to a logic HIGH level, this programs the counter to divide-by 28 (256). Apply a trigger pulse and clock in 255 pulses, this sets all flip-flop stages to a logic HIGH level. Set S3 to a logic HIGH level, this causes the counter to divide-by

224. Clock one more pulse into the RS input, this causes a logic 0 to ripple through the counter and output Q/Q goes from HIGH-to-LOW level. This method of testing the delay counter is faster than clocking in 224 (16 777 216) clock pulses.

FUNCTION TABLE

Notes

1. H = HIGH voltage level L = LOW voltage level X = don't care

↑ = LOW-to-HIGH transition ↓ = HIGH-to-LOW transition.

INPUTS OUTPUTS

MR A

BQQ

HXXLH

L↑X one HIGH level

output pulse

one LOW level

output pulse

LX↓one HIGH level

output pulse

one LOW level

output pulse

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Philips Semiconductors Product speciﬁcation

Programmable delay timer with oscillator 74HC/HCT5555

DELAY TIME SELECTION

SELECT INPUTS OUTPUT Q/Q (FREQUENCY DIVIDING)

BINARY DECIMAL

LLLL2

LLLH2

LLHL2

LLHH2

LHLL2

LHLH2

LHHL2

128

LHHH2

256

..... .

HLLL2

131 072

HLLH2

262 144

HLHL2

524 288

HLHH2

1 048 576

HHLL2

2 097 152

HHLH2

4 194 304

HHHL2

8 388 608

HHHH2

16 777 216

Fig.5 Timing diagram.

Timing example shown for S3, S2, S1, S0 = 0011 (binary 24, decimal 16).

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