Philips 74HCT4520U, 74HCT4520N, 74HCT4520DB, 74HCT4520D, 74HC4520U Datasheet

DATA SH EET

Product specification
File under Integrated Circuits, IC06

December 1990

INTEGRATED CIRCUITS

74HC/HCT4520

Dual 4-bit synchronous binary
counter

For a complete data sheet, please also download:

•The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications

•The IC06 74HC/HCT/HCU/HCMOS Logic Package Information

•The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines

December 1990 2

Philips Semiconductors Product specification

Dual 4-bit synchronous binary counter 74HC/HCT4520

FEATURES

• Output capability: standard

• ICC category: MSI

GENERAL DESCRIPTION

The 74HC/HCT4520 are high-speed Si-gate CMOS
devices and are pin compatible with the “4520” of the
“4000B” series. They are specified in compliance with
JEDEC standard no. 7A.

The 74HC/HCT4520 are dual 4-bit internally synchronous
binary counters with an active HIGH clock input (nCP

0

)

and an active LOW clock input (nCP1), buffered outputs

from all four bit positions (nQ0 to nQ3) and an active HIGH
overriding asynchronous master reset input (nMR).

The counter advances on either the LOW-to-HIGH
transition of nCP0 if nCP1 is HIGH or the HIGH-to-LOW
transition of nCP1 if nCP0 is LOW. Either nCP0 or nCP

1

may be used as the clock input to the counter and the other
clock input may be used as a clock enable input. A HIGH
on nMR resets the counter (nQ0 to nQ3= LOW)
independent of nCP0 and nCP1.

APPLICATIONS

• Multistage synchronous counting

• Multistage asynchronous counting

• Frequency dividers

QUICK REFERENCE DATA

GND = 0 V; T

amb

=25°C; tr=tf= 6 ns

Notes

1. C

PD

is used to determine the dynamic power dissipation (PD in µW):

PD=CPD× V

CC

2

× fi+∑(CL× V

CC

2

× fo) where:
fi= input frequency in MHz
fo= output frequency in MHz
∑ (CL× V

CC

2

× fo) = sum of outputs
CL= output load capacitance in pF
VCC= supply voltage in V

2. For HC the condition is VI= GND to V

CC

For HCT the condition is VI= GND to VCC− 1.5 V

ORDERING INFORMATION

See

“74HC/HCT/HCU/HCMOS Logic Package Information”

.

SYMBOL PARAMETER CONDITIONS

TYPICAL

UNIT

HC HCT

t

PHL

/ t

PLH

propagation delay nCP0, nCP1 to nQ

n

CL= 15 pF; VCC=5 V2424ns

t

PHL

propagation delay nMR to nQ

n

13 13 ns

f

max

maximum clock frequency 68 64 MHz

C

I

input capacitance 3.5 3.5 pF

C

PD

power dissipation capacitance per counter notes 1 and 2 29 24 pF

December 1990 3

Philips Semiconductors Product specification

Dual 4-bit synchronous binary counter 74HC/HCT4520

PIN DESCRIPTION

PIN NO. SYMBOL NAME AND FUNCTION

1, 9 1CP

0

, 2CP

0

clock inputs (LOW-to-HIGH, edge-triggered)

2, 10 1

CP1, 2CP

1

clock inputs (HIGH-to-LOW, edge-triggered)

3, 4, 5, 6 1Q

0

to 1Q

3

data outputs
7, 15 1MR, 2MR asynchronous master reset inputs (active HIGH)
8 GND ground (0 V)
11, 12, 13, 14 2Q

0

to 2Q

3

data outputs
16 V

CC

positive supply voltage

Fig.1 Pin configuration. Fig.2 Logic symbol. Fig.3 IEC logic symbol.