Philips 74HCT4514U, 74HCT4514PW, 74HCT4514N3, 74HCT4514N, 74HCT4514DB Datasheet

DATA SH EET

Product specification
File under Integrated Circuits, IC06

September 1993

INTEGRATED CIRCUITS

74HC/HCT4514

4-to-16 line decoder/demultiplexer
with input latches

For a complete data sheet, please also download:

•The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications

•The IC06 74HC/HCT/HCU/HCMOS Logic Package Information

•The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines

September 1993 2

Philips Semiconductors Product specification

4-to-16 line decoder/demultiplexer with
input latches

74HC/HCT4514

FEATURES

• Non-inverting outputs

• Output capability: standard

• ICC category: MSI

GENERAL DESCRIPTION

The 74HC/HCT4514 are high-speed Si-gate CMOS
devices and are pin compatible with “4514” of the “4000B”
series. They are specified in compliance with JEDEC
standard no. 7A.

The 74HC/HCT4514 are 4-to-16 line
decoders/demultiplexers having four binary weighted
address inputs (A

0

to A3), with latches, a latch enable input
(LE), and an active LOW enable input (E). The 16 outputs
(Q0to Q15) are mutually exclusive active HIGH. When LE
is HIGH, the selected output is determined by the data on
An. When LE goes LOW, the last data present at Anare
stored in the latches and the outputs remain stable. When
E is LOW, the selected output, determined by the contents
of the latch, is HIGH. At E HIGH, all outputs are LOW. The
enable input (E) does not affect the state of the latch.

When the “4514” is used as a demultiplexer, E is the data
input and A0to A3are the address inputs.

QUICK REFERENCE DATA

GND = 0 V; T

amb

=25°C; tr=tf= 6 ns

Notes

1. C

PD

is used to determine the dynamic power dissipation (PD in µW):

PD=CPD× V

CC

2

× fi+∑ (CL× V

CC

2

× fo) where:
fi= input frequency in MHz
fo= output frequency in MHz
∑ (CL× V

CC

2

× fo) = sum of outputs
CL= output load capacitance in pF
VCC= supply voltage in V

2. For HC the condition is VI= GND to V

CC

For HCT the condition is VI= GND to VCC− 1.5 V

ORDERING INFORMATION

See

“74HC/HCT/HCU/HCMOS Logic Package Information”

.

SYMBOL PARAMETER CONDITIONS

TYPICAL

UNIT

HC HCT

t

PHL

/ t

PLH

propagation delay An to Q

n

CL= 15 pF; VCC=5 V 23 26 ns

C

I

input capacitance 3.5 3.5 pF

C

PD

power dissipation capacitance per package notes 1 and 2 44 45 pF

September 1993 3

Philips Semiconductors Product specification

4-to-16 line decoder/demultiplexer with
input latches

74HC/HCT4514

PIN DESCRIPTION

PIN NO. SYMBOL NAME AND FUNCTION

1 LE latch enable input (active HIGH)
2, 3, 21, 22 A

0

to A

3

address inputs

11, 9, 10, 8, 7, 6, 5, 4, 18, 17, 20, 19, 14, 13, 16, 15 Q

0

to Q

15

multiplexer outputs (active HIGH)
12 GND ground (0 V)
23

E enable input (active LOW)

24 V

CC

positive supply voltage

Fig.1 Pin configuration. Fig.2 Logic symbol. Fig.3 IEC logic symbol.