December 1990 2
Philips Semiconductors Product specification
8-channel analog
multiplexer/demultiplexer with latch
74HC/HCT4351
FEATURES
• Wide analog input voltage range:
± 5 V
• Low “ON” resistance:
80 Ω (typ.) at VCC− VEE= 4.5 V
70 Ω (typ.) at VCC− VEE= 6.0 V
60 Ω (typ.) at VCC− VEE= 9.0 V
• Logic level translation: to enable 5 V logic to
communicate with ± 5 V analog signals
• Typical “break before make” built in
• Address latches provided
• Output capability: non-standard
• ICC category: MSI
GENERAL DESCRIPTION
The 74HC/HCT4351 are high-speed Si-gate CMOS
devices. They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT4351 are 8-channel analog
multiplexers/demultiplexers with three select inputs (S
0
to
S2), two enable inputs (E1and E2), a latch enable input
(LE), eight independent inputs/outputs (Y0to Y7) and a
common input/output (Z).
With E1LOW and E2is HIGH, one of the eight switches is
selected (low impedance ON-state) by S0to S2. The data
at the select inputs may be latched by using the active
LOW latch enable input (LE). When LE is HIGH the latch
is transparent. When either of the two enable inputs,
E1(active LOW) and E2(active HIGH), is inactive, all 8
analog switches are turned off.
VCCand GND are the supply voltage pins for the digital
control inputs (S0to S2, LE, E1and E2). The VCCto GND
ranges are 2.0 to 10.0 V for HC and 4.5 to 5.5 V for HCT.
The analog inputs/outputs (Y0to Y7, and Z) can swing
between VCCas a positive limit and VEEas a negative
limit.
VCC− VEEmay not exceed 10.0 V.
For operation as a digital multiplexer/demultiplexer, VEEis
connected to GND (typically ground).
QUICK REFERENCE DATA
VEE= GND = 0 V; T
amb
=25°C; tr=tf= 6 ns
SYMBOL PARAMETER CONDITIONS
TYPICAL
UNIT
HC HCT
t
PZH
/ t
PZL
turn “ON” time E1, E2or Snto V
os
CL= 15 pF; RL=1 kΩ; VCC=5 V2735ns
t
PHZ
/ t
PLZ
turn “OFF” time E1, E2or Snto V
os
21 23 ns
C
I
input capacitance 3.5 3.5 pF
C
PD
power dissipation capacitance per switch notes 1 and 2 25 25 pF
C
S
max. switch capacitance
independent (Y) 5 5 pF
common (Z) 25 25 pF
Notes
1. CPD is used to determine the dynamic power
dissipation (PD in µW):
PD=CPD× V
CC
2
× fi+∑ {(CL+ C
S
)
× V
CC
2
× fo}
where:
fi= input frequency in MHz
fo= output frequency in MHz
CL= output load capacitance in pF
CS= max. switch capacitance in pF
∑ {(CL+ C
S
)
× V
CC
2
× fo} = sum of outputs
VCC= supply voltage in V
2. For HC the condition is VI= GND to V
CC
For HCT the condition is VI= GND to VCC− 1.5 V
ORDERING INFORMATION
See
“74HC/HCT/HCU/HCMOS Logic Package
Information”
.