Philips 74HCT377U, 74HCT377PW, 74HCT377N, 74HCT377DB, 74HCT377D Datasheet

DATA SH EET

Product specification
File under Integrated Circuits, IC06

December 1990

INTEGRATED CIRCUITS

74HC/HCT377

Octal D-type flip-flop with data
enable; positive-edge trigger

For a complete data sheet, please also download:

•The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications

•The IC06 74HC/HCT/HCU/HCMOS Logic Package Information

•The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines

December 1990 2

Philips Semiconductors Product specification

Octal D-type flip-flop with data enable;
positive-edge trigger

74HC/HCT377

FEATURES

• Ideal for addressable register applications

• Data enable for address and data synchronization

applications

• Eight positive-edge triggered D-type flip-flops

• See “273” for master reset version

• See “373” for transparent latch version

• See “374” for 3-state version

• Output capability: standard

• ICC category: MSI

GENERAL DESCRIPTION

The 74HC/HCT377 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.

The 74HC/HCT377 have eight edge-triggered, D-type
flip-flops with individual D inputs and Q outputs. A common
clock (CP) input loads all flip-flops simultaneously when
the data enable (E) is LOW. The state of each D input, one
set-up time before the LOW-to-HIGH clock transition, is
transferred to the corresponding output (Qn) of the flip-flop.

TheE input must be stable only one set-up time prior to the
LOW-to-HIGH transition for predictable operation.

QUICK REFERENCE DATA

GND = 0 V; T

amb

=25°C; tr=tf= 6 ns

Notes

1. C

PD

is used to determine the dynamic power dissipation (PD in µW):

PD=CPD× V

CC

2

× fi+∑ (CL× V

CC

2

× fo) where:
fi= input frequency in MHz
fo= output frequency in MHz
∑ (CL× V

CC

2

× fo) = sum of outputs
CL= output load capacitance in pF
VCC= supply voltage in V

2. For HC the condition is VI= GND to V

CC

For HCT the condition is VI= GND to VCC− 1.5 V

ORDERING INFORMATION

See

“74HC/HCT/HCU/HCMOS Logic Package Information”

.

SYMBOL PARAMETER CONDITIONS

TYPICAL

UNIT

HC HCT

t

PHL

/ t

PLH

propagation delay CP to Q

n

CL= 15 pF; VCC= 5 V 13 14 ns

f

max

maximum clock frequency 77 53 MHz

C

I

input capacitance 3.5 3.5 pF

C

PD

power dissipation capacitance per flip-flop notes 1 and 2 20 20 pF

December 1990 3

Philips Semiconductors Product specification

Octal D-type flip-flop with data enable;
positive-edge trigger

74HC/HCT377

PIN DESCRIPTION

PIN NO. SYMBOL NAME AND FUNCTION

1

E data enable input (active LOW)

2, 5, 6, 9, 12, 15, 16, 19 Q

0

to Q

7

flip-flop outputs

3, 4, 7, 8, 13, 14, 17, 18 D

0

to D

7

data inputs
10 GND ground (0 V)
11 CP clock input (LOW-to-HIGH, edge-triggered)
20 V

CC

positive supply voltage

Fig.1 Pin configuration. Fig.2 Logic symbol. Fig.3 IEC logic symbol.