Philips 74HCT366N, 74HCT366D, 74HCT366U, 74HC366N, 74HC366D Datasheet
DATA SH EET
Product specification
File under Integrated Circuits, IC06
December 1990
INTEGRATED CIRCUITS
74HC/HCT366
Hex buffer/line driver; 3-state;
inverting
For a complete data sheet, please also download:
•The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
•The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
•The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
December 1990 2
Philips Semiconductors Product specification
Hex buffer/line driver; 3-state; inverting 74HC/HCT366
FEATURES
• Inverting outputs
• Output capability: bus driver
• ICC category: MSI
GENERAL DESCRIPTION
The 74HC/HCT366 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT366 are hex inverting buffer/line drivers
with 3-state outputs. The 3-state outputs (nY) are
controlled by the output enable inputs (
OE1, OE2).
A HIGH on OEncauses the outputs to assume a high
impedance OFF-state.
The ”366” is identical to the “365” but has inverting outputs.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25 °C; tr= tf= 6 ns
Notes
1. C
PD
is used to determine the dynamic power dissipation (PDin µW):
PD= CPD× V
CC
2
× fi+∑(CL× V
CC
2
× fo) where:
fi= input frequency in MHz
fo= output frequency in MHz
∑ (CL× V
CC
2
× fo) = sum of outputs
CL= output load capacitance in pF
VCC= supply voltage in V
2. For HC the condition is VI= GND to V
CC
For HCT the condition is VI= GND to VCC− 1.5 V
ORDERING INFORMATION
See
“74HC/HCT/HCU/HCMOS Logic Package Information”
.
SYMBOL PARAMETER CONDITIONS
TYPICAL
UNIT
HC HCT
t
PHL
/ t
PLH
propagation delay
nA to nY
CL= 15 pF; VCC= 5 V 10 11 ns
C
I
input capacitance 3.5 3.5 pF
C
PD
power dissipation capacitance per buffer notes 1 and 2 30 30 pF
December 1990 3
Philips Semiconductors Product specification
Hex buffer/line driver; 3-state; inverting 74HC/HCT366
PIN DESCRIPTION
PIN NO. SYMBOL NAME AND FUNCTION
1, 15
OE1, OE
2
output enable inputs (active LOW)
2, 4, 6, 10, 12, 14 1A to 6A data inputs
3, 5, 7, 9, 11, 13 1
Y to 6Y data outputs
8 GND ground (0 V)
16 V
CC
positive supply voltage
Fig.1 Pin configuration. Fig.2 Logic symbol. Fig.3 IEC logic symbol.
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