Philips 74HCT165U, 74HCT165PW, 74HCT165N, 74HCT165DB, 74HC165DB Datasheet
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DATA SH EET
Product specification
File under Integrated Circuits, IC06
December 1990
INTEGRATED CIRCUITS
74HC/HCT165
8-bit parallel-in/serial-out shift
register
For a complete data sheet, please also download:
•The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
•The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
•The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
December 1990 2
Philips Semiconductors Product specification
8-bit parallel-in/serial-out shift register 74HC/HCT165
FEATURES
• Asynchronous 8-bit parallel load
• Synchronous serial input
• Output capability: standard
• ICC category: MSI
GENERAL DESCRIPTION
The 74HC/HCT165 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT165 are 8-bit parallel-load or serial-in shift
registers with complementary serial outputs (Q
7
and
Q7) available from the last stage. When the parallel load
(PL) input is LOW, parallel data from the D0to
D7inputs are loaded into the register asynchronously.
When PL is HIGH, data enters the register serially at the
Dsinput and shifts one place to the right
(Q0→ Q1→ Q2, etc.) with each positive-going clock
transition. This feature allows parallel-to-serial converter
expansion by tying the Q7output to the DSinput of the
succeeding stage.
The clock input is a gated-OR structure which allows one
input to be used as an active LOW clock enable (CE) input.
The pin assignment for the CP and CE inputs is arbitrary
and can be reversed for layout convenience. The
LOW-to-HIGH transition of input CE should only take
place while CP HIGH for predictable operation. Either the
CP or the CE should be HIGH before the
LOW-to-HIGH transition of PL to prevent shifting the data
when PL is activated.
APPLICATIONS
• Parallel-to-serial data conversion
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25 °C; tr= tf= 6 ns
Notes
1. C
PD
is used to determine the dynamic power dissipation (PDin µW):
PD= CPD× V
CC
2
× fi+∑(CL× V
CC
2
× fo) where:
fi= input frequency in MHz
fo= output frequency in MHz
∑ (CL× V
CC
2
× fo) = sum of outputs
CL= output load capacitance in pF
VCC= supply voltage in V
2. For HC the condition is VI= GND to V
CC
For HCT the condition is VI= GND to VCC− 1.5 V
ORDERING INFORMATION
See
“74HC/HCT/HCU/HCMOS Logic Package Information”
.
SYMBOL PARAMETER CONDITIONS
TYPICAL
UNIT
HC HCT
t
PHL
/ t
PLH
propagation delay
CP to Q7,Q
7
PL to Q7,Q
7
D7 to Q7,Q
7
CL= 15 pF; VCC= 5 V
16
15
11
14
17
11
ns
ns
ns
f
max
maximum clock frequency 56 48 MHz
C
I
input capacitance 3.5 3.5 pF
C
PD
power dissipation capacitance per
package
notes 1 and 2 35 35 pF
December 1990 3
Philips Semiconductors Product specification
8-bit parallel-in/serial-out shift register 74HC/HCT165
PIN DESCRIPTION
PIN NO. SYMBOL NAME AND FUNCTION
1
PL asynchronous parallel load input (active LOW)
7
Q
7
complementary output from the last stage
9Q
7
serial output from the last stage
2 CP clock input (LOW-to-HIGH edge-triggered)
8 GND ground (0 V)
10 D
s
serial data input
11, 12, 13, 14, 3, 4, 5, 6 D
0
to D
7
parallel data inputs
15
CE clock enable input (active LOW)
16 V
CC
positive supply voltage
Fig.1 Pin configuration. Fig.2 Logic symbol. Fig.3 IEC logic symbol.
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