Philips 74HCT160U, 74HCT160PW, 74HCT160N, 74HCT160D, 74HC160U Datasheet

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DATA SH EET
Product specification File under Integrated Circuits, IC06
December 1990
INTEGRATED CIRCUITS
74HC/HCT160
Presettable synchronous BCD decade counter; asynchronous reset
For a complete data sheet, please also download:
The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
December 1990 2
Philips Semiconductors Product specification
Presettable synchronous BCD decade counter; asynchronous reset
74HC/HCT160
FEATURES
Synchronous counting and loading
Two count enable inputs for n-bit cascading
Positive-edge triggered clock
Asynchronous reset
Output capability: standard
ICC category: MSI
GENERAL DESCRIPTION
The 74HC/HCT160 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A.
The 74HC/HCT160 are synchronous presettable decade counters which feature an internal look-ahead carry and can be used for high-speed counting. Synchronous operation is provided by having all flip-flops clocked simultaneously on the positive-going edge of the clock (CP). The outputs (Q
0
to Q3) of the counters may be preset to a
HIGH or LOW level. A LOW level at the parallel enable
input (PE) disables the counting action and causes the data at the data inputs (D0 to D3) to be loaded into the counter on the positive-going edge of the clock (providing that the set-up and hold time requirements forPE are met). Preset takes place regardless of the levels at count enable inputs (CEP and CET).
A LOW level at the master reset input (MR) sets all four outputs of the flip-flops (Q0 to Q3) to LOW level regardless of the levels at CP, PE, CET and CEP inputs (thus providing an asynchronous clear function).
The look-ahead carry simplifies serial cascading of the counters. Both count enable inputs (CEP and CET) must be HIGH to count. The CET input is fed forward to enable the terminal count output (TC). The TC output thus enabled will produce a HIGH output pulse of a duration approximately equal to a HIGH level output of Q0. This pulse can be used to enable the next cascaded stage.
The maximum clock frequency for the cascaded counters is determined by the CP to TC propagation delay and CEP to CP set-up time, according to the following formula:
f
max
=
1
t
P max()
CP to TC()+tSU(CEP to CP)
---------------------------------------------------------------------------------------------------------
QUICK REFERENCE DATA
GND = 0 V; T
amb
=25°C; tr=tf= 6 ns
SYMBOL PARAMETER CONDITIONS
TYPICAL
UNIT
HC HCT
t
PHL
propagation delay
CP to Q
n
CP to TC MR to Q
n
MR to TC CET to TC
CL=15pF; VCC=5V 19
21 21 21 14
21 24 23 26 14
ns ns ns ns ns
t
PLH
propagation delay
CP to Q
n
CP to TC CET to TC
19 21 14
21 20 7
ns ns ns
f
max
maximum clock frequency
61 31 MHz
C
I
input capacitance 3.5 3.5 pF
C
PD
power dissipation capacitance per package
notes 1 and 2
39 34 pF
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW):
PD=CPD× V
CC
2
× fi+
(C V
CC
2
× fo)
where:
fi= input frequency in MHz fo= output frequency in MHz (C V
CC
2
× fo) = sum of outputs CL= output load capacitance in pF VCC= supply voltage in V
2. For HC the condition is VI= GND to V
CC
For HCT the condition is
VI= GND to VCC− 1.5 V
December 1990 3
Philips Semiconductors Product specification
Presettable synchronous BCD decade counter; asynchronous reset
74HC/HCT160
ORDERING INFORMATION
See
“74HC/HCT/HCU/HCMOS Logic Package Information”
.
PIN DESCRIPTION
PIN NO. SYMBOL NAME AND FUNCTION
1
MR asynchronous master reset (active LOW) 2 CP clock input (LOW-to-HIGH, edge-triggered) 3, 4, 5, 6 D
0
to D
3
data inputs 7 CEP count enable input 8 GND ground (0 V) 9
PE parallel enable input (active LOW) 10 CET count enable carry input 14, 13, 12, 11 Q
0
to Q
3
flip-flop outputs 15 TC terminal count output 16 V
CC
positive supply voltage
Fig.1 Pin configuration. Fig.2 Logic symbol. Fig.3 IEC logic symbol.
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