Philips 74HCT139U, 74HCT139PW, 74HCT139NB, 74HCT139DB, 74HC139U Datasheet
...
DATA SH EET
Product specification
File under Integrated Circuits, IC06
September 1993
INTEGRATED CIRCUITS
74HC/HCT139
Dual 2-to-4 line
decoder/demultiplexer
For a complete data sheet, please also download:
•The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
•The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
•The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
September 1993 2
Philips Semiconductors Product specification
Dual 2-to-4 line decoder/demultiplexer 74HC/HCT139
FEATURES
• Demultiplexing capability
• Two independent 2-to-4 decoders
• Multifunction capability
• Active LOW mutually exclusive outputs
• Output capability: standard
• ICCcategory: MSI
GENERAL DESCRIPTION
The 74HC/HCT139 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). It is specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT139 are high-speed, dual 2-to-4 line
decoder/multiplexers. This device has two independent
decoders, each accepting two binary weighted inputs
(nA0and nA1) and providing four mutually exclusive active
LOW outputs (nY0 to nY3). Each decoder has an active
LOW enable input (nE).
When nE is HIGH, every output is forced HIGH. The
enable can be used as the data input for a 1-to-4
demultiplexer application.
The “139” is identical to the HEF4556 of the HE4000B
family.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25 °C; tr= tf= 6 ns
Notes
1. C
PD
is used to determine the dynamic power dissipation (PDin µW):
PD= CPD× V
CC
2
× fi+∑(CL× V
CC
2
× fo) where:
fi= input frequency in MHz
fo= output frequency in MHz
∑ (CL× V
CC
2
× fo) = sum of outputs
CL= output load capacitance in pF
VCC= supply voltage in V
2. For HC the condition is VI= GND to V
CC
For HCT the condition is VI= GND to VCC− 1.5 V
APPLICATIONS
• Memory decoding or data-routing
• Code conversion
ORDERING INFORMATION
See
“74HC/HCT/HCU/HCMOS Logic Package Information”
.
SYMBOL PARAMETER CONDITIONS
TYPICAL
UNIT
HC HCT
t
PHL
/ t
PLH
propagation delay CL= 15 pF; VCC= 5 V
nA
n
to nY
n
11 13 ns
n
E3to nY
n
10 13 ns
C
I
input capacitance 3.5 3.5 pF
C
PD
power dissipation capacitance per multiplexer notes 1 and 2 42 44 pF
September 1993 3
Philips Semiconductors Product specification
Dual 2-to-4 line decoder/demultiplexer 74HC/HCT139
PIN DESCRIPTION
PIN NO. SYMBOL NAME AND FUNCTION
1, 15 1
E, 2E enable inputs (active LOW)
2, 3 1A
0
, 1A
1
address inputs
4, 5, 6, 7 1
Y0to 1Y
3
outputs (active LOW)
8 GND ground (0 V)
12, 11, 10, 9 2
Y0to 2Y
3
outputs (active LOW)
14, 13 2A
0
, 2A
1
address inputs
16 V
CC
positive supply voltage
Fig.1 Pin configuration.
Fig.2 Logic symbol.
Fig.3 IEC logic symbol.
(a) (b)
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