Philips 74HCT137NB, 74HCT137D, 74HC137U, 74HC137N, 74HC137DB Datasheet

DATA SH EET

Product specification
File under Integrated Circuits, IC06

December 1990

INTEGRATED CIRCUITS

74HC/HCT137

3-to-8 line decoder/demultiplexer
with address latches; inverting

For a complete data sheet, please also download:

•The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications

•The IC06 74HC/HCT/HCU/HCMOS Logic Package Information

•The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines

December 1990 2

Philips Semiconductors Product specification

3-to-8 line decoder/demultiplexer with
address latches; inverting

74HC/HCT137

FEATURES

• Combines 3-to-8 decoder with 3-bit latch

• Multiple input enable for easy expansion or independent

controls

• Active LOW mutually exclusive outputs

• Output capability: standard

• ICC category: MSI

GENERAL DESCRIPTION

The 74HC/HCT137 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.

The 74HC/HCT137 are 3-to-8 line decoder/demultiplexers
with latches at the three address inputs (A

n

). The “137”
essentially combines the 3-to-8 decoder function with a
3-bit storage latch. When the latch is enabled (LE = LOW),
the “137” acts as a 3-to-8 active LOW decoder. When the
latch enable (LE) goes from LOW-to-HIGH, the last data
present at the inputs before this transition, is stored in the
latches. Further address changes are ignored as long as
LE remains HIGH.

The output enable input (E1 and E2) controls the state of
the outputs independent of the address inputs or latch
operation. All outputs are HIGH unless E1 is LOW and E

2

is HIGH.
The “137” is ideally suited for implementing

non-overlapping decoders in 3-state systems and strobed
(stored address) applications in bus oriented systems.

QUICK REFERENCE DATA

GND = 0 V; T

amb

=25°C; tr=tf= 6 ns

Notes

1. C

PD

is used to determine the dynamic power dissipation (PD in µW):

PD=CPD× V

CC

2

× fi+ ∑ (CL× V

CC

2

× fo) where:
fi= input frequency in MHz
fo= output frequency in MHz
∑ (CL× V

CC

2

× fo) = sum of outputs
CL= output load capacitance in pF
VCC= supply voltage in V

2. For HC the condition is VI= GND to V

CC

For HCT the condition is VI= GND to VCC− 1.5 V

ORDERING INFORMATION

See

“74HC/HCT/HCU/HCMOS Logic Package Information”

.

SYMBOL PARAMETER CONDITIONS

TYPICAL

UNIT

HC HCT

t

PHL/ tPLH

propagation delay CL= 15 pF; VCC=5 V

A

n

to Y

n

18 19 ns

LE to Y

n

17 21 ns

E1 to Y

n

15 17 ns

E

2

to Y

n

15 15 ns

C

I

input capacitance 3.5 3.5 pF

C

PD

power dissipation capacitance per package notes 1 and 2 57 59 pF

December 1990 3

Philips Semiconductors Product specification

3-to-8 line decoder/demultiplexer with
address latches; inverting

74HC/HCT137

PIN DESCRIPTION

PIN NO. SYMBOL NAME AND FUNCTION

1, 2, 3 A

0

to A

2

data inputs

4

LE latch enable input (active LOW)

5

E

1

data enable input (active LOW)

6E

2

data enable input (active HIGH)
8 GND ground (0 V)
15, 14, 13, 12, 11, 10, 9, 7

Y0 to Y

7

multiplexer outputs
16 V

CC

positive supply voltage

Fig.1 Pin configuration. Fig.2 Logic symbol.

Fig.3 IEC logic symbol. Fig.4 Functional diagram.