Philips 74HC00, 74HCT00 Technical data

74HC00

INTEGRATED CIRCUITS

DATA SHEET

74HC00; 74HCT00

Quad 2-input NAND gate

Product speciﬁcation			2003 Jun 30
Supersedes data of 1997 Aug 26

Philips Semiconductors	Product speciﬁcation

Quad 2-input NAND gate	74HC00; 74HCT00

FEATURES

∙Complies with JEDEC standard no. 8-1A

∙ESD protection:

HBM EIA/JESD22-A114-A exceeds 2000 V MM EIA/JESD22-A115-A exceeds 200 V

∙Specified from −40 to +85 °C and −40 to +125 °C.

QUICK REFERENCE DATA

GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns.

DESCRIPTION

The 74HC00/74HCT00 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A.

The 74HC00/74HCT00 provide the 2-input NAND function.

SYMBOL	PARAMETER	CONDITIONS	TYPICAL		UNIT

			74HC00	74HCT00
			74HC00	74HCT00

tPHL/tPLH	propagation delay nA, nB to nY	CL = 15 pF; VCC = 5 V	7	10	ns
CI	input capacitance		3.5	3.5	pF
CPD	power dissipation capacitance per gate	notes 1 and 2	22	22	pF

Notes

1.CPD is used to determine the dynamic power dissipation (PD in μW). PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where:

fi = input frequency in MHz; fo = output frequency in MHz;

CL = output load capacitance in pF; VCC = supply voltage in Volts;

N = total load switching outputs;

Σ(CL × VCC2 × fo) = sum of the outputs.

2.For 74HC00 the condition is VI = GND to VCC.

For 74HCT00 the condition is VI = GND to VCC − 1.5 V.

FUNCTION TABLE

See note 1.

INPUT		OUTPUT

nA	nB	nY

L	L	H

L	H	H

H	L	H

H	H	L

Note

1. H = HIGH voltage level; L = LOW voltage level.

2003 Jun 30

Philips Semiconductors

Product speciﬁcation

Quad 2-input NAND gate

74HC00; 74HCT00

ORDERING INFORMATION

PACKAGE

TYPE NUMBER

TEMPERATURE

PINS

PACKAGE

MATERIAL

CODE

RANGE

74HC00N

−40 to +125 °C

DIP14

plastic

SOT27-1

74HCT00N

−40 to +125 °C

DIP14

plastic

SOT27-1

74HC00D

−40 to +125 °C

SO14

plastic

SOT108-1

74HCT00D

−40 to +125 °C

SO14

plastic

SOT108-1

74HC00DB

−40 to +125 °C

SSOP14

plastic

SOT337-1

74HCT00DB

−40 to +125 °C

SSOP14

plastic

SOT337-1

74HC00PW

−40 to +125 °C

TSSOP14

plastic

SOT402-1

74HCT00PW

−40 to +125 °C

TSSOP14

plastic

SOT402-1

74HC00BQ

−40 to +125 °C

DHVQFN14

plastic

SOT762-1

74HCT00BQ

−40 to +125 °C

DHVQFN14

plastic

SOT762-1

PINNING

SYMBOL

DESCRIPTION

data input

handbook, halfpage

VCC

data output

data input

data output

GND

ground (0 V)

data output

data input

GND

data input

MNA210

data output

data input

Fig.1 Pin configuration DIP14, SO14 and

data input

(T)SSOP14.

VCC

supply voltage

2003 Jun 30

Philips Semiconductors	Product speciﬁcation

Quad 2-input NAND gate	74HC00; 74HCT00

handbook, halfpage		1A	VCC
		1	14
1B	2			13	4B
1Y	3			12	4A
2A	4	GND(1)		11	4Y
2B	5			10	3B
2Y	6			9	3A
		7	8
	Top view	GND	3Y	MNA950
	Top view			MNA950

(1)The die substrate is attached to this pad using conductive die attach material. It can not be used as a supply pin or input.

Fig.2 Pin configuration DHVQFN14.

handbook, halfpage A

MNA211

Fig.3 Logic diagram (one gate).

						handbook, halfpage	1		&	3
							2		&	3
handbook, halfpage							2
1		1A
				1Y	3
2		1B		1Y	3		4
2		1B

4		2A							&	6
									&

				2Y	6		5
	5	2B		2Y	6		5


	9	3A
	9	3A
10		3B		3Y	8			9	&	8
10		3B					10		&	8
							10
12		4A
				4Y	11
13		4B		4Y	11		12
13		4B
									&	11

							13

			MNA212

									MNA246

Fig.4 Function diagram.

Fig.5 IEC logic symbol.

2003 Jun 30

Philips Semiconductors

Product speciﬁcation

Quad 2-input NAND gate

74HC00; 74HCT00

RECOMMENDED OPERATING CONDITIONS

SYMBOL

PARAMETER

CONDITIONS

74HC00

74HCT00

UNIT

MIN.

TYP.

MAX.

MIN.

TYP.

MAX.

VCC

supply voltage

2.0

5.0

6.0

4.5

5.0

5.5

input voltage

−

VCC

−

VCC

output voltage

−

VCC

−

VCC

Tamb

operating ambient

see DC and AC

−40

+25

+125

−40

+25

+125

°C

temperature

characteristics per

device

tr, tf

input rise and fall times

VCC = 2.0 V

−

1000

−

VCC = 4.5 V

−

6.0

500

−

6.0

500

VCC = 6.0 V

−

400

−

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 60134); voltages are referenced to GND (ground = 0 V).

SYMBOL	PARAMETER	CONDITIONS	MIN.	MAX.	UNIT

VCC	supply voltage		−0.5	+7.0	V
IIK	input diode current	VI < −0.5 V or VI > VCC + 0.5 V	−	±20	mA
IOK	output diode current	VO < −0.5 V or VO > VCC + 0.5 V	−	±20	mA
IO	output source or sink	−0.5 V < VO < VCC + 0.5 V	−	±25	mA
	current

ICC, IGND	VCC or GND current		−	±50	mA
Tstg	storage temperature		−65	+150	°C
Ptot	power dissipation	Tamb = −40 to +125 °C; note 1	−	500	mW

Note

1.For DIP14 packages: above 70 °C derate linearly with 12 mW/K. For SO14 packages: above 70 °C derate linearly with 8 mW/K.

For SSOP14 and TSSOP14 packages: above 60 °C derate linearly with 5.5 mW/K. For DHVQFN14 packages: above 60 °C derate linearly with 4.5 mW/K.

2003 Jun 30

Philips Semiconductors	Product speciﬁcation

Quad 2-input NAND gate	74HC00; 74HCT00

DC CHARACTERISTICS

Type 74HC00

At recommended operating conditions; voltages are referenced to GND (ground = 0 V).

SYMBOL	PARAMETER	TEST CONDITIONS		MIN.	TYP.	MAX.	UNIT

		OTHER	VCC (V)
		OTHER	VCC (V)

Tamb = −40 to +85 °C; note 1

VIH	HIGH-level input voltage		2.0	1.5	1.2	−	V
			4.5	3.15	2.4	−	V

			6.0	4.2	3.2	−	V

VIL	LOW-level input voltage		2.0	−	0.8	0.5	V
			4.5	−	2.1	1.35	V

			6.0	−	2.8	1.8	V

VOH	HIGH-level output voltage	VI = VIH or VIL
		IO = −20 μA	2.0	1.9	2.0	−	V
		IO = −20 μA	4.5	4.4	4.5	−	V
		IO = −20 μA	6.0	5.9	6.0	−	V
		IO = −4.0 mA	4.5	3.84	4.32	−	V
		IO = −5.2 mA	6.0	5.34	5.81	−	V
VOL	LOW-level output voltage	VI = VIH or VIL
		IO = 20 μA	2.0	−	0	0.1	V
		IO = 20 μA	4.5	−	0	0.1	V
		IO = 20 μA	6.0	−	0	0.1	V
		IO = 4.0 mA	4.5	−	0.15	0.33	V
		IO = 5.2 mA	6.0	−	0.16	0.33	V
ILI	input leakage current	VI = VCC or GND	6.0	−	−	±1.0	μA
IOZ	3-state output OFF current	VI = VIH or VIL;	6.0	−	−	±.5.0	μA
		VO = VCC or GND
ICC	quiescent supply current	VI = VCC or GND; IO = 0	6.0	−	−	20	μA

2003 Jun 30

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