Philips 74HC00, 74HCT00 Technical data

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74HC00; 74HCT00

Quad 2-input NAND gate

Product specification
Supersedes data of 1997 Aug 26

2003 Jun 30

Philips Semiconductors Product specification

Quad 2-input NAND gate 74HC00; 74HCT00

FEATURES

• Complies with JEDEC standard no. 8-1A

• ESD protection:

HBM EIA/JESD22-A114-A exceeds 2000 V
MM EIA/JESD22-A115-A exceeds 200 V

• Specified from −40 to +85 °C and −40 to +125 °C.

DESCRIPTION

The 74HC00/74HCT00 are high-speed Si-gate CMOS
devices and are pin compatible with low power Schottky
TTL (LSTTL). They are specified in compliance with
JEDEC standard no. 7A.

The 74HC00/74HCT00 provide the 2-input NAND
function.

QUICK REFERENCE DATA

GND = 0 V; T

=25°C; tr=tf= 6 ns.

amb

SYMBOL PARAMETER CONDITIONS

t

PHL/tPLH

C

I

C

PD

propagation delay nA, nB to nY CL= 15 pF; VCC= 5 V 7 10 ns
input capacitance 3.5 3.5 pF
power dissipation capacitance per gate notes 1 and 2 22 22 pF

Notes

1. C

is used to determine the dynamic power dissipation (PDin µW).

PD

PD=CPD× V

2

× fi× N+Σ(CL× V

CC

2

× fo) where:

CC

fi= input frequency in MHz;
fo= output frequency in MHz;

= output load capacitance in pF;

C

L

VCC= supply voltage in Volts;
N = total load switching outputs;
Σ(CL× V

2

× fo) = sum of the outputs.

CC

2. For 74HC00 the condition is VI= GND to VCC.
For 74HCT00 the condition is VI= GND to VCC− 1.5 V.

TYPICAL

UNIT

74HC00 74HCT00

FUNCTION TABLE

See note 1.

INPUT OUTPUT

nA nB nY

LLH

LHH
HLH
HHL

Note

1. H = HIGH voltage level;
L = LOW voltage level.

2003 Jun 30 2

Philips Semiconductors Product specification

Quad 2-input NAND gate 74HC00; 74HCT00

ORDERING INFORMATION

PACKAGE

TYPE NUMBER

74HC00N −40to+125°C 14 DIP14 plastic SOT27-1
74HCT00N −40 to +125 °C 14 DIP14 plastic SOT27-1
74HC00D −40to+125°C 14 SO14 plastic SOT108-1
74HCT00D −40 to +125 °C 14 SO14 plastic SOT108-1
74HC00DB −40 to +125 °C 14 SSOP14 plastic SOT337-1
74HCT00DB −40 to +125 °C 14 SSOP14 plastic SOT337-1
74HC00PW −40 to +125 °C 14 TSSOP14 plastic SOT402-1
74HCT00PW −40 to +125 °C 14 TSSOP14 plastic SOT402-1
74HC00BQ −40 to +125 °C 14 DHVQFN14 plastic SOT762-1
74HCT00BQ −40 to +125 °C 14 DHVQFN14 plastic SOT762-1

TEMPERATURE

RANGE

PINS PACKAGE MATERIAL CODE

PINNING

PIN SYMBOL DESCRIPTION

1 1A data input
2 1B data input
3 1Y data output
4 2A data input
5 2B data input
6 2Y data output
7 GND ground (0 V)
8 3Y data output

9 3A data input
10 3B data input
11 4Y data output
12 4A data input
13 4B data input
14 V

CC

supply voltage

handbook, halfpage

1A
1B
1Y
2A
2B
2Y

GND

1
2
3
4

00

5
6
7

14
13
12
11
10

9
8

MNA210

Fig.1 Pin configuration DIP14, SO14 and

(T)SSOP14.

V
4B
4A
4Y
3B
3A
3Y

CC

2003 Jun 30 3

Philips Semiconductors Product specification

Quad 2-input NAND gate 74HC00; 74HCT00

V

handbook, halfpage

1B

2

1A

CC

114

13

4B

3

1Y

4

2A

5

2B

6

2Y

Top view

(1) The die substrate is attached to this pad using conductive die

attach material. It can not be used as a supply pin or input.

(1)

GND

7

GND 3Y

8

12

11

10

9

MNA950

4A

4Y

3B

3A

Fig.2 Pin configuration DHVQFN14.

handbook, halfpage

1

1B

2

4

2B

5

1Y1A3

2Y2A6

handbook, halfpage

handbook, halfpage

A

Y

B

MNA211

Fig.3 Logic diagram (one gate).

1
2

4
5

&

&

3

6

9

3B

10

12

4B

13

3Y3A8

4Y4A11

MNA212

Fig.4 Function diagram.

2003 Jun 30 4

9

10

12
13

&

&

MNA246

8

11

Fig.5 IEC logic symbol.

Philips Semiconductors Product specification

Quad 2-input NAND gate 74HC00; 74HCT00

RECOMMENDED OPERATING CONDITIONS

SYMBOL PARAMETER CONDITIONS

UNIT

MIN. TYP. MAX. MIN. TYP. MAX.

74HC00 74HCT00

V

CC

V

I

V

O

T

amb

supply voltage 2.0 5.0 6.0 4.5 5.0 5.5 V
input voltage 0 − V
output voltage 0 − V
operating ambient

temperature

see DC and AC
characteristicsper

−40 +25 +125 −40 +25 +125 °C

0 − V

CC

0 − V

CC

CC
CC

V
V

device

t

r,tf

input rise and fall times VCC= 2.0 V −−1000 −−−ns

= 4.5 V − 6.0 500 − 6.0 500 ns

V

CC

V

= 6.0 V −−400 −−−ns

CC

LIMITING VALUES

In accordance with theAbsolute Maximum Rating System (IEC 60134); voltages are referenced to GND (ground = 0 V).

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

V

CC

I

IK

I

OK

I

O

supply voltage −0.5 +7.0 V
input diode current VI< −0.5 V or VI>VCC+ 0.5 V −±20 mA
output diode current VO< −0.5 V or VO>VCC+ 0.5 V −±20 mA
output source or sink

−0.5V<VO<VCC+ 0.5 V −±25 mA

current

I

, I

CC

T

stg

P

tot

GNDVCC

or GND current −±50 mA
storage temperature −65 +150 °C
power dissipation T

= −40 to +125 °C; note 1 − 500 mW

amb

Note

1. For DIP14 packages: above 70 °C derate linearly with 12 mW/K.
For SO14 packages: above 70 °C derate linearly with 8 mW/K.
For SSOP14 and TSSOP14 packages: above 60 °C derate linearly with 5.5 mW/K.
For DHVQFN14 packages: above 60 °C derate linearly with 4.5 mW/K.

2003 Jun 30 5

Philips Semiconductors Product specification

Quad 2-input NAND gate 74HC00; 74HCT00

DC CHARACTERISTICS
Type 74HC00

At recommended operating conditions; voltages are referenced to GND (ground=0V).

SYMBOL PARAMETER

T

= −40 to +85 °C; note 1

amb

V

IH

V

IL

V

OH

V

OL

I

LI

I

OZ

I

CC

HIGH-level input voltage 2.0 1.5 1.2 − V

LOW-level input voltage 2.0 − 0.8 0.5 V

HIGH-level output voltage VI=VIH or V

LOW-level output voltage VI=VIH or V

input leakage current VI=VCC or GND 6.0 −−±1.0 µA
3-state output OFF current VI=VIH or VIL;

quiescent supply current VI=VCC or GND; IO= 0 6.0 −−20 µA

TEST CONDITIONS

MIN. TYP. MAX. UNIT

OTHER V

CC

(V)

4.5 3.15 2.4 − V

6.0 4.2 3.2 − V

4.5 − 2.1 1.35 V

6.0 − 2.8 1.8 V

IL

IO= −20 µA 2.0 1.9 2.0 − V
I

= −20 µA 4.5 4.4 4.5 − V

O

I

= −20 µA 6.0 5.9 6.0 − V

O

I

= −4.0 mA 4.5 3.84 4.32 − V

O

I

= −5.2 mA 6.0 5.34 5.81 − V

O

IL

IO=20µA 2.0 − 0 0.1 V
I

=20µA 4.5 − 0 0.1 V

O

I

=20µA 6.0 − 0 0.1 V

O

I

= 4.0 mA 4.5 − 0.15 0.33 V

O

I

= 5.2 mA 6.0 − 0.16 0.33 V

O

6.0 −−±.5.0 µA

VO=VCC or GND

2003 Jun 30 6