Philips 74f862, 74f863 DATASHEETS
INTEGRATED CIRCUITS
74F862, 74F863
Bus transceivers (3-State)
Product specification
Supersedes data of 1999 Jan 08
IC15 Data Handbook
2000 Mar 24
Philips Semiconductors Product specification
Bus transceivers (3-State)
FEA TURES
•Provide high performance bus interface buffering for wide
data/address paths or buses carrying parity
•High impedance NPN base inputs for reduced loading (20µA in
High and Low states)
•I
is 20µA vs. 1000µA for AM29861 series
IL
•Buffered control inputs for light loading, or increased fan-in as
required with MOS microprocessors
•Positive and negative over-shoots are clamped to ground
•3-State outputs glitch free during power-up and power-down
•Slim dual In-line (DIP) 300mil package
•Broadside pinout compatible with AMD AM29862–29863
•Outputs sink 64mA
DESCRIPTION
The 74F862 and 74F863 bus transceivers provide high performance
bus interface buffering for wide data/address paths of buses carrying
parity. The 74F863 9-bit bus transceiver has NOR-ed transmit and
receive output enables for maximum control flexibility.
TYPE
PROPAGATION
DELA Y
74F862 6.0ns 150mA
74F863 6.0ns 115mA
TYPICAL
TYPICAL SUPPL Y
CURRENT
(TOTAL)
74F862, 74F863
ORDERING INFORMATION
COMMERCIAL RANGE
PACKAGES
24-pin Plastic Slim
Dual In-line (300mil)
Package
24-pin Plastic Small
Outline Large
1
NOTE:
1. Thermal mounting techniques are recommended. See SMD
Process Applications for a discussion of thermal considerations for
surface mounted devices.
PIN CONFIGURATION
OEBA
1
A
2
0
A
3
1
A
4
2
A
5
3
A
6
4
A
7
5
A
8
6
A
9
7
A
10
8
A
11
9
GND
12
V
= 5V±10%;
CC
T
= 0°C to +70°C
a
PKG DWG #
N74F862N, N74F863N SOT222-1
N74F862D, N74F863D SOT137-1
V
24
CC
B
23
0
B
22
1
B
21
2
B
20
3
B
19
4
B
18
5
B
17
6
B
16
7
B
15
8
B
14
9
OEAB
13
TOP VIEW
SF00518
2000 Mar 24 853-0881 23378
2
Philips Semiconductors Product specification
Bus transceivers (3-State)
PIN CONFIGURATION
74F862
OEBA
1
2
A
0
3
A
1
4
A
2
5
A
3
6
A
4
7
A
5
8
A
6
9
A
7
10
A
8
11
A
9
GND
12
TOP VIEW
LOGIC SYMBOL
74F862
234567891011
A
A
0
1A2A3A4A5A6A7A8A9
13
OEAB
OEBA
1
B0B1B2B3B4B5B6B7B8B
24
23
22
21
20
19
18
17
16
15
14
13
SF00521
V
CC
B
0
B
1
B
2
B
3
B
4
B
5
B
6
B
7
B
8
B
9
OEAB
9
PIN CONFIGURA TION
GND
1
0
2
A
0
3
A
1
4
A
2
5
A
3
6
A
4
7
A
5
8
A
6
9
A
7
10
A
8
11
1
12
TOP VIEW
OEBA
OEBA
LOGIC SYMBOL
2345678910
A
A
0
1
OEBA
11
14
13
0
OEBA
1
OEAB
0
OEAB
1
B0B1B2B3B4B5B6B7B
74F862, 74F863
74F863
24
V
23
B
22
B
21
B
20
B
19
B
18
B
17
B
16
B
15
B
14
OEAB
13
OEAB
SF01441
74F863
1A2A3A4A5A6A7A8
CC
0
1
2
3
4
5
6
7
8
0
1
8
23 22 21 2019 18 1716 15 14
VCC= Pin 24
GND = Pin 12
LOGIC SYMBOL (IEEE/IEC)
1
13
2
3
4
5
6
7
8
9
10
11
74F862
EN1(BA)
EN2(AB)
∆
1
∆
23 22 21 2019 18 1716 15
SF00525
SF00522
VCC= Pin 24
GND = Pin 12
LOGIC SYMBOL (IEEE/IEC)
1
11
14
13
∆
2
23
∆
22
21
20
19
18
17
16
15
14
SF00523
2
3
4
5
6
7
8
9
10
11
74F863
&
&
∆
1
EN1(BA)
EN2(AB)
∆
∆
2
23
∆
22
21
20
19
18
17
16
15
14
SF00526
2000 Mar 24
3
Philips Semiconductors Product specification
74F862
74F863
Bus transceivers (3-State)
LOGIC DIAGRAM
74F862
OEAB
10 10
A
OEBA
n
SF00531
B
n
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
PINS DESCRIPTION
A0 – A
9
B0 – B
9
OEBA Transmit output enable input 1.0/0.033 20µA/20µA
OEAB Receive output enable input 1.0/0.033 20µA/20µA
A0 – A
9
B0 – B
9
A0 – A
9
B0 – B
9
OEBA
n
OEAB
n
A0 – A
9
B0 – B
9
NOTE: One (1.0) FAST Unit Load is defined as: 20µA in the High state and 0.6mA in the Low state.
Data transmit inputs 3.5/0.1 17 70µA/70µA
Data receive inputs 3.5/0.1 17 70µA/70µA
Data transmit outputs 1200/106.7 24mA/64mA
Data receive outputs 1200/106.7 24mA/64mA
Data transmit inputs 3.5/0.1 17 70µA/70µA
Data receive inputs 3.5/0.1 17 70µA/70µA
Transmit output enable input 1.0/0.033 20µA/20µA
Receive output enable input 1.0/0.033 20µA/20µA
Data transmit outputs 1200/106.7 24mA/64mA
Data receive outputs 1200/106.7 24mA/64mA
LOGIC DIAGRAM
OEAB
OEAB
OEBA
OEBA
74F862, 74F863
74F863
0
1
99
A
n
0
1
74F(U.L.)
HIGH/LOW
B
n
SF00532
LOAD VALUE
HIGH/LOW
FUNCTION TABLE FOR 74F862
INPUTS OPERATING MODES
OEAB OEBA 74F862
L H A data to B bus
H L B bus to A data
H H Z
H = High voltage level
L = Low voltage level
Z = High impedance “off” state
FUNCTION TABLE FOR 74F863
INPUTS OPERATING MODES
OEAB
L
L0
H
X
H H H H Z
H = High voltage level
L = Low voltage level
Z = High impedance “off” state
OEAB
0
L
L
X
H
OEBA
1
H
X
L
L
OEBA
0
1
X
H
L
L
74F863
A data to B bus
B bus to A data
2000 Mar 24
4
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