Philips 74f862, 74f863 DATASHEETS

INTEGRATED CIRCUITS

74F862, 74F863

Bus transceivers (3-State)

Product specification

2000 Mar 24

Supersedes data of 1999 Jan 08

IC15 Data Handbook

P s

on o s

Philips Semiconductors Product specification

Bus transceivers (3-State)	74F862, 74F863

FEATURES

•Provide high performance bus interface buffering for wide data/address paths or buses carrying parity

•High impedance NPN base inputs for reduced loading (20μA in High and Low states)

•IIL is 20μA vs. 1000μA for AM29861 series

•Buffered control inputs for light loading, or increased fan-in as required with MOS microprocessors

•Positive and negative over-shoots are clamped to ground

•3-State outputs glitch free during power-up and power-down

•Slim dual In-line (DIP) 300mil package

•Broadside pinout compatible with AMD AM29862±29863

•Outputs sink 64mA

DESCRIPTION

The 74F862 and 74F863 bus transceivers provide high performance bus interface buffering for wide data/address paths of buses carrying parity. The 74F863 9-bit bus transceiver has NOR-ed transmit and receive output enables for maximum control flexibility.

TYPE	TYPICAL	TYPICAL SUPPLY
	PROPAGATION	CURRENT
	DELAY	(TOTAL)
74F862	6.0ns	150mA
74F863	6.0ns	115mA

ORDERING INFORMATION

		COMMERCIAL RANGE
	PACKAGES	VCC = 5V±10%;	PKG DWG #
		Ta = 0°C to +70°C
	24-pin Plastic Slim
	Dual In-line (300mil)	N74F862N, N74F863N	SOT222-1
	Package
	24-pin Plastic Small	N74F862D, N74F863D	SOT137-1
	Outline Large1

NOTE:

1. Thermal mounting techniques are recommended. See SMD

Process Applications for a discussion of thermal considerations for surface mounted devices.

PIN CONFIGURATION

					VCC
OEBA		1		24
A0					B0
		2		23
A1					B1
		3		22
A2					B2
		4		21
A3					B3
		5		20
A4					B4
		6		19
A5					B5
		7		18
A6					B6
		8		17
A7					B7
		9		16
A8					B8
		10		15
A9					B9
		11		14
GND
		12		13		OEAB

TOP VIEW

SF00518

2000 Mar 24

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853-0881 23378

Philips Semiconductors	Product specification
Bus transceivers (3-State)	74F862, 74F863

PIN CONFIGURATION											PIN CONFIGURATION
				74F862											74F863
													0	1		24	VCC
	OEBA		1		24		VCC					OEBA
												A0		2		23	B0
	A0		2		23		B0
												A1		3		22	B1
	A1		3		22		B1
	A2		4		21		B2					A2		4		21	B2
												A3		5		20	B3
	A3		5		20		B3
	A4		6		19		B4					A4		6		19	B4
	A5		7		18		B5					A5		7		18	B5
												A6		8		17	B6
	A6		8		17		B6
												A7		9		16	B7
	A7		9		16		B7
												A8		10		15	B8
	A8		10		15		B8
	A9		11		14		B9					OEBA	1	11		14		OEAB	0
												GND
														12		13			1
	GND		12		13			OEAB										OEAB
				TOP VIEW		SF00521									TOP VIEW		SF01441

LOGIC SYMBOL

										74F862
			2				3		4	5		6	7		8		9		10 11
					A0 A1 A2 A3 A4 A5 A6 A7 A8 A9
		13			OEAB
		1			OEBA
					B0 B1 B2 B3 B4 B5 B6 B7 B8 B9
			23 22 21 20 19 18 17 16 15 14
VCC	=	Pin 24
GND	=	Pin 12																	SF00522

LOGIC SYMBOL

									74F863
			2				3	4	5		6	7		8		9	10
					A0 A1 A2 A3 A4 A5 A6 A7 A8
		1			OEBA0
		11			OEBA1
		14			OEAB0
		13			OEAB1
					B0 B1 B2 B3 B4 B5 B6 B7 B8
			23 22 21 20 19 18 17 16 15
VCC	=	Pin 24
GND	=	Pin 12

SF00525

LOGIC SYMBOL (IEEE/IEC)

		74F862
	1	EN1(BA)
	13
		EN2(AB)
	2	1
		2
	3
	4
	5
	6
	7
	8
	9
	10
	11

LOGIC SYMBOL (IEEE/IEC)

	1
	11
	14
	13
23	2
22	3
21	4
20	5
19	6
18	7
17	8
16	9
15	10
14	11
	SF00523

74F863

&

EN1(BA)

& EN2(AB)

23

1

2

22

21

20

19

18

17

16

15

14

SF00526

2000 Mar 24

3

Philips Semiconductors	Product specification
Bus transceivers (3-State)	74F862, 74F863

LOGIC DIAGRAM

LOGIC DIAGRAM

74F862

74F863

0

OEAB

OEAB

1

10

10

OEAB

9

9

An

Bn

An

Bn

0

OEBA

OEBA

1

SF00531

OEBA

SF00532

INPUT AND OUTPUT LOADING AND FAN-OUT TABLE

PINS

DESCRIPTION

74F(U.L.)

LOAD VALUE

HIGH/LOW

HIGH/LOW

A0 ± A9

Data transmit inputs

3.5/0.117

70μA/70μA

B0 ± B9

Data receive inputs

3.5/0.117

70μA/70μA

Transmit output enable input

1.0/0.033

20μA/20μA

74F862

OEBA

Receive output enable input

1.0/0.033

20μA/20μA

OEAB

A0 ± A9

Data transmit outputs

1200/106.7

24mA/64mA

B0 ± B9

Data receive outputs

1200/106.7

24mA/64mA

A0 ± A9

Data transmit inputs

3.5/0.117

70μA/70μA

B0 ± B9

Data receive inputs

3.5/0.117

70μA/70μA

n

Transmit output enable input

1.0/0.033

20μA/20μA

74F863

OEBA

n

Receive output enable input

1.0/0.033

20μA/20μA

OEAB

A0 ± A9

Data transmit outputs

1200/106.7

24mA/64mA

B0 ± B9

Data receive outputs

1200/106.7

24mA/64mA

NOTE: One (1.0) FAST Unit Load is defined as: 20μA in the High state and 0.6mA in the Low state.

FUNCTION TABLE FOR 74F862

				INPUTS				OPERATING MODES
								74F862
			OEAB			OEBA
			L			H		A data to B bus
			H			L		B bus to A data
			H			H		Z
H	=	High voltage level
L	=	Low voltage level
Z	=	High impedance ªoffº state

FUNCTION TABLE FOR 74F863

INPUTS

OPERATING MODES

0

1

0

1

74F863

OEAB

OEAB

OEBA

OEBA

L

L

H

X

A data to B bus

L0

L

X

H

H

X

L

L

B bus to A data

X

H

L

L

H

H

H

H

Z

H

=

High voltage level

L

=

Low voltage level

Z

= High impedance ªoffº state

2000 Mar 24

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