74f841
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74F841/842/843/845/846
Bus interface latches
Product specification
Replaces datasheet 74F841/842/843/844/845/846 of 1999 Jan 08
IC15 Data Handbook
1999 Jun 23
INTEGRATED CIRCUITS
Philips Semiconductors Product specification
74F841/74F842/74F843/
74F845/74F846
Bus interface latches
74F841/74F842 10-bit bus interface latches, non-inverting/inverting (3-State)
74F843 9-bit bus interface latch, non-inverting (3-State)
74F845/74F846 8-bit bus interface latches, non-inverting/inverting (3-State)
2
1999 Jun 23 853–1208 21851
FEA TURES
•High speed parallel latches
•Extra data width for wide address/data paths or buses carrying
parity
•High impedance NPN base input structure minimizes bus loading
•IIL is 20µA vs 1000A for AM29841 series
•Buffered control inputs to reduce AC effects
•Ideal where high speed, light loading, or increased fan-in are
required as with MOS microprocessors
•Positive and negative over-shoots are clamped to ground
•3-State outputs glitch free during power-up and power-down
•48mA sink current
•Slim dual in-line 300 mil package
•Broadside pinout
•Pin-for-pin and function compatible with AMD AM29841-846
series
TYPE
TYPICAL
PROPAGATION
DELA Y
TYPICAL
SUPPLY CURRENT
(TOTAL)
74F841, 74F842 5.5ns 60mA
74F843, 74F845 5.5ns 75mA
74F846 6.2ns 60mA
DESCRIPTION
The 74F841–74F846 bus interface latch series are designed to
provide extra data width for wider address/data paths of buses
carrying parity.
The 74F841–74F846 series are funcitonally an pin compatible to the
AMD AM29841–AM29846 series.
The 74F841 consists of ten D-type latches with 3-State outputs. The
flip-flops appear transparent to the data when Latch Enable (LE) is
High. This allows asynchronous operation, as the output transition
follows the data in transition. On the LE High-to-Low transition, the
data that meets the setup and hold time is latched.
Data appears on the bus when the Output Enable (OE
) is Low.
When OE
is High the output is in the High-impedance state.
The 74F842 is the inverted output version of the 74F841.
The 74F843 consists of nine D-type latches with 3-State outputs. In
addition to the LE and OE
pins, the 74F843 has a Master Reset
(MR
) pin and Preset (PRE) pin. These pins are ideal for parity bus
interfacing in high performance systems. When MR
is Low, the
outputs are Low if OE
is Low. When MR is High, data can be
entered into the latch. When PRE
is Low, the outputs are High, if OE
is Low, PRE overrides MR.
The 74F845 consists of eight D-type latches with 3-State outputs. In
addition to the LE, OE
, MR and PRE pins, the 74F845 has two
addtitional OE
pins making a total of three Output Enables (OE0,
OE
1, OE2) pins.
The multiple Ouptut Enables (OE
0, OE1, OE2) allow multi-user
control of the interface, e.g., CS
, DMA, and RD/WR.
The 74F846 is the inverted output version of the 74F845.
ORDERING INFORMATION
PACKAGES
COMMERCIAL RANGE
V
CC
= 5V±10%; T
amb
= 0°C to +70°C
PACKAGE DRAWING
NUMBER
24-pin plastic Slim DIP (300 mil) N74F841N, N74F842N, N74F843N, N74F845N, N74F846N SOT222-1
24-pin plastic SOL N74F841D, N74F842D, N74F843D, N74F845D, N74F846D SOT137-1
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
PINS DESCRIPTION
74F(U.L.)
HIGH/LOW
LOAD VALUE
HIGH/LOW
Dn Data inputs 1.0/0.033 20µA/20µA
LE Latch Enable input 1.0/0.033 20µA/20µA
OE, OEn Output Enable input (active Low) 1.0/0.033 20µA/20µA
MR Master Reset input (active Low) 1.0/0.033 20µA/20µA
PRE Preset input (active Low) 1.0/0.033 20µA/20µA
Qn Data outputs 1200/80 24mA/48mA
Qn Data outputs 1200/80 24mA/48mA
NOTE: One (1.0) FAST Unit Load is defined as: 20µA in the High state and 0.6mA in the Low state.
Philips Semiconductors Product specification
74F841/74F842/74F843/
74F845/74F846
Bus interface latches
1999 Jun 23
3
PIN CONFIGURATION for 74F841
1
2
3
4
5
6
7
8
9
10
11
12 13
14
15
16
17
18
19
20
21
22
23
24
OE
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
V
CC
Q0
Q1
Q2
Q3
Q4
Q5
Q7
Q6
Q8
Q9
LE
GND
SF01279
LOGIC SYMBOL for 74F841
13
2
SF01280
3456 78910
1
D0
LE
D1 D2 D3 D4 D5 D6 D7 D8
OE
V
CC
= Pin 24
GND = Pin 12
11
D9
23 22 21 20 19 18 17 16 15 14
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9
LOGIC SYMBOL (IEEE/IEC) for 74F841
1
15
18
19
20
21
232
1 D
SF01281
16
17
5
6
7
8
9
10
4
13
EN
C1
223
1411
PIN CONFIGURATION for 74F842
1
2
3
4
5
6
7
8
9
10
11
12 13
14
15
16
17
18
19
20
21
22
23
24
OE
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
V
CC
Q0
Q
1
Q
2
Q
3
Q
4
Q
5
Q
7
Q6
Q
8
Q
9
LE
GND
SF01282
LOGIC SYMBOL for 74F842
13
2
SF01283
3456 78910
1
D0
LE
D1 D2 D3 D4 D5 D6 D7 D8
OE
V
CC
= Pin 24
GND = Pin 12
11
D9
23 22 21 20 19 18 17 16 15 14
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9
LOGIC SYMBOL (IEEE/IEC) for 74F842
1
15
18
19
20
21
232
1 D
SF01284
16
17
5
6
7
8
9
10
4
13
EN
C1
223
14
11
Philips Semiconductors Product specification
74F841/74F842/74F843/
74F845/74F846
Bus interface latches
1999 Jun 23
4
PIN CONFIGURATION for 74F843
1
2
3
4
5
6
7
8
9
10
11
12 13
14
15
16
17
18
19
20
21
22
23
24
OE
D0
D1
D2
D3
D4
D5
D6
D7
D8
MR
V
CC
Q0
Q1
Q2
Q3
Q4
Q5
Q7
Q6
Q8
PRE
LE
GND
SF01285
LOGIC SYMBOL for 74F843
13
2
SF01286
3456 78910
D0
LE
D1 D2 D3 D4 D5 D6 D7 D8
V
CC
= Pin 24
GND = Pin 12
23 22 21 20 19 18 17 16 15
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8
14 PRE
11 MR
1OE
LOGIC SYMBOL (IEEE/IEC) for 74F843
1
15
18
19
20
21
232
1 D
SF01287
16
17
5
6
7
8
9
10
4
11
14
13
EN
R
C1
S2
223
Philips Semiconductors Product specification
74F841/74F842/74F843/
74F845/74F846
Bus interface latches
1999 Jun 23
5
PIN CONFIGURATION for 74F845
1
2
3
4
5
6
7
8
9
10
11
12 13
14
15
16
17
18
19
20
21
22
23
24
OE
0
OE
1
D0
D1
D2
D3
D4
D5
D6
D7
MR
V
CC
OE2
Q0
Q1
Q2
Q3
Q4
Q6
Q5
Q7
PRE
LE
GND
SF01291
LOGIC SYMBOL for 74F845
13
SF01292
3456 78910
D0
LE
D1 D2 D3 D4 D5 D6 D7
V
CC
= Pin 24
GND = Pin 12
22 21 20 19 18 17 16 15
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
14 PRE
11 MR
1 OE0
2 OE1
23 OE2
LOGIC SYMBOL (IEEE/IEC) for 74F845
1
15
18
19
20
21
223
1 D
SF01293A
16
17
5
6
7
8
9
10
4
2
23
14
S2
11
R
13
C1
&
EN
PIN CONFIGURATION for 74F846
1
2
3
4
5
6
7
8
9
10
11
12 13
14
15
16
17
18
19
20
21
22
23
24
OE
0
OE
1
D0
D1
D2
D3
D4
D5
D6
D7
MR
V
CC
OE2
Q
0
Q
1
Q
2
Q
3
Q
4
Q
6
Q
5
Q
7
PRE
LE
GND
SF01294
LOGIC SYMBOL for 74F846
13
SF01295
3456 78910
D0
LE
D1 D2 D3 D4 D5 D6 D7
V
CC
= Pin 24
GND = Pin 12
22 21 20 19 18 17 16 15
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
14 PRE
11 MR
1 OE0
2 OE1
23 OE2
LOGIC SYMBOL (IEEE/IEC) for 74F846
1
15
18
19
20
21
223
1 D
SF01296A
16
17
5
6
7
8
9
10
4
2
23
14
S2
11
R
13
C1
&
EN
Philips Semiconductors Product specification
74F841/74F842/74F843/
74F845/74F846
Bus interface latches
1999 Jun 23
6
LOGIC DIAGRAM for 74F841
1
OE
V
CC
= Pin 24
GND = Pin 12
LQ
D
Q0
23
13
LE
D0
2
LQ
D
Q1
22
D1
3
LQ
D
Q2
21
D2
4
LQ
D
Q3
20
D3
5
LQ
D
Q4
19
D4
6
LQ
D
Q5
18
D5
7
LQ
C
D
Q6
17
D6
8
LQ
D
Q7
16
D7
9
LQ
D
Q8
15
D8
10
LQ
D
Q9
14
D9
11
SF01297
LOGIC DIAGRAM for 74F842
1
OE
V
CC
= Pin 24
GND = Pin 12
LQ
D
Q0
23
13
LE
D0
2
LQ
D
Q1
22
D1
3
LQ
D
Q2
21
D2
4
LQ
D
Q3
20
D3
5
LQ
D
Q4
19
D4
6
LQ
D
Q5
18
D5
7
LQ
C
D
Q6
17
D6
8
LQ
D
Q7
16
D7
9
LQ
D
Q8
15
D8
10
LQ
D
Q9
14
D9
11
SF01298
FUNCTION TABLE for 74F841 and 74F842
OUTPUTS
INPUTS
74F841 74F842
OPERATING MODE
OE LE Dn Qn Qn
L H L L H
p
L H H H L
Transparent
L ↓ l L H
L ↓ h H L
Latched
H X X Z Z High Impedance
L L X NC NC Hold
H = High voltage level
L = Low voltage level
h = High state one setup time before the High-to-Low LE transition
l = Low state one setup time before the High-to-Low LE transition
↓ = High-to-Low transition
X = Don’t care
NC= No change
Z = High impedance “off” state
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