Philips 74f808, 74f1808 DATASHEETS

INTEGRATED CIRCUITS

74F808, 74F1808

Hex 2-input AND drivers

Product specification IC15 Data Handbook

 

1991 Jan 02

Philips Semiconductors Product specification

74F808/74F1808Hex 2-input AND drivers

FEA TURES

•High capacitive drive capability

•Choice of configuration

Corner V Center V

and GND – 74F808

CC

and GND – 74F1808

CC

•Typical propagation delay of 4.0ns

•Superior ground noise characteristics (implemented using output

edge rate control)

•Increased source and sink current (64mA)

TYPICAL

PROPAGATION

TYPE

DELA Y

74F808 4.0ns 24mA

74F1808 4.0ns 24mA

ORDERING INFORMATION

ORDER CODE

DESCRIPTION COMMERCIAL RANGE

V

= 5V ±10%,

CC

T

= 0°C to +70°C

amb

20–pin plastic DIP N74F808N, N74F1808N SOT 146-1

20–pin plastic SOL N74F808D, N74F1808D SOT163-1

TYPICAL SUPPL Y

CURRENT

( TOTAL)

PKG DWG #

PIN CONFIGURATION

D0a

1

D0b

2 3

Q0

4

D1a

5

D1b

6

Q1

7

D2a

8

D2b

9

Q2

10 11

GND

LOGIC SYMBOL

1245781213

74F808

20

V

CC

19

D5b

18

D5a

17

Q5

16

D4b

15

D4a

14

Q4

13

D3b

12

D3a Q3

SF00474

15 16 18 19

INPUT AND OUTPUT LOADING AND FAN OUT TABLE

PINS DESCRIPTION 74F

Dna – Dnb Data inputs 1.0/0.033 20µA/20µA

Q0 – Q5 Data outputs 3200/106.764mA/64mA

NOTE: One (1.0) FAST unit load is defined as: 20µA in the high state and 0.6mA in the low state.

(U.L.) HIGH/

LOW

LOAD VALUE

HIGH/LOW

D0a D0bD1a D2a D2b D3aD3bD1b

V

= Pin 20

CC

GND = Pin 10

IEC/IEEE SYMBOL

1 2 4 5 7

8 12 13 15 16 18 19

Q0 Q1 Q2 Q3

36 911

74F808

&

D4aD4bD5aD5b

Q4 Q5

14 17

SF00475

3

6

9

11

14

17

SF00476

January 2, 1991 853-1528 01346

2

Philips Semiconductors Product specification

Hex 2-input AND drivers

PIN CONFIGURATION

74F1808

1

D4b

2

Q

5

3

D5a

4

D5b

5

V

CC

6

D0a

7

D0b

8

Q

0

D1a

9

D1b

10 11

LOGIC SYMBOL

74F1808

6791012131718

D0a D0bD1a D2a D2b D3a D3bD1b

Q0 Q1 Q2 Q3

8111416

V

= Pin 5

CC

GND = Pin 15

20

D4a

19

4

Q

18

D3b

17

D3a

16

Q

3

15

GND

14

Q

2

13

D2b

12

D2a

1

Q

SF00477

20 1 3 4

D4a D4bD5a D5b

Q4 Q5

2

19

SF00478

LOGIC DIAGRAM

74F808

1

D0a

2

Dob

4

D1a

5

D1b

7

D2a

8

D2b

12

D3a

13

D3b

15

D4a

16

D4b

18

D5a

19

D5b

VCC = Pin 20 GND = Pin 10

3

6

9

11

14

17

FUNCTION TABLE

INPUTS OUTPUT

Da Db Q

H H H

L X L

X L L

NOTES:

H = High voltage level L = Low voltage level X = Don’t care

74F808/74F1808

74F1808

6

D0a

QO

Q1

Q2

Q3

Q4

Q5

7

Dob

9

D1a

10

D1b

12

D2a

13

D2b

17

D3a

18

D3b

20

D4a

1

D4b

3

D5a

4

D5b V

= Pin 5

CC

GND = Pin 15

8

11

14

16

19

2

SF00480

QO

Q1

Q2

Q3

Q4

Q5

IEC/IEEE SYMBOL

6 7

9 10 12 13 17 18 20

1

3

4

January 2, 1991

74F1808

&

8

11

14

16

19

2

SF00479

3