Philips 74f807 DATASHEETS

Philips Semiconductors FAST Products Product specification
FAST 74F807
Octal shift/count registered transceiver with adder and parity (3–State)
1
June 18, 1991 853–1421 02931

FEATURES

positive edge–triggered D–type flip–flops
High speed full adder
8–bit parity generator
High impedance PNP inputs for light
bus loading
Center V
CC
and GND pins and con­trolled output buffers minimize ground–bounce problems
3–State glitch–free power–up and
power–down
Broadside pinout

DESCRIPTION

The 74F807 is a registered transceiver that also has the capability to perform count, shift, and add functions. It is also has the capability to generate a parity bit output. All of this is done within a 28–pin package.
The MR
input is an overriding asynchronous reset which forces the STATOUT output low as well as the A and B busses.
The A and B busses have separate OE inputs (OEA, OEB]. These inputs have no bearing on the internal functioning of
this device only on the output states. Both OE
pins are enabled low.
All operating modes, other than clear, 3–State, and the two hold modes re­quire the rising edge of the clock. All setup and hold times must be observed for proper functioning.
Data on the internal register can be switched on either the A or B ports for output.
Depeding on the state of the select in­puts (S0, S1, S2), and carry in/ serial in/ clock enable (CI/SI/CE), the 74F807 has nine distinct operating modes:
1. Add mode w/carry in – the CI/SI/CE input is used as a carry in signal and the STATOUT output is the carry out signal. (In add mode the COUT is NOT registered. This means the carry output signal appears at the STATOUT output one clock prior to the related data.). In this mode, the CI/SI/CE input is added to the register contents and to the inputs. (The adder uses only the An inputs, not the Bn inputs.)
2. Add mode wo/carry in –– same as above except the CI/SI/CE input is not included in the addition.
3. Count w/count enable (count) –– the CI/SI/ CE input is now used as the count enable
input and the STATOUT output is terminal count. In this mode the CI/SI/CE input must be high to enable the count function. The register contents are incremented by one.
4. Count w/count enable (hold) –– same as above except no incrementing occurs.
5. Count wo/count enable –– same as num­ber 3 except the CI/SI/CE input has no con­trol over counting or holding.
6. Shift –– The CI/SI/CE input now becomes the serial input and the STATOUT output becomes the serial output. In this mode the CI/SI/CE input is shifted into the Q0 register, Q0 into the Q1 register etc. The Q7 register is shifted into the STATOUT.
7. Load A inputs –– The CI/SI/CE input has no bearing in either of the load modes. The STATOUT output becomes the parity out. The parity out is high for an odd number of registered bits high, and low for even number of registered bits high (even parity). In this mode the An inputs are loaded into the internal register and output to the B bus. If OEA
= low the internal register would wrap
around and be loaded again.
8. Load B inputs –– same as number 7 except the A and B busses are switched.
9. Hold –– Again the CI/SI/CE input is not used; the STATOUT output is still the parity out. In this mode either the A bus, B bus or both can be held with the registered data. No other operation is performed.
TYPE
TYPICAL f
max
TYPICAL SUPPLY CURRENT (TOTAL)
74F807 115MHz 155mA

ORDERING INFORMATION

ORDER CODE
DESCRIPTION COMMERCIAL RANGE
V
CC
= 5V ±10%, T
amb
= 0°C to +70°C
28–pin plastic DIP (300 mils) N74F807N
28–pin SOL
1
N74F807D
28–pin PLCC N74F807A
Note to ordering information
1.Thermal mounting techiques are recommended. See SMD Process Applications (page 17) for a discussion of thermal consideration for surface
mounted devices.

Philips Semiconductors FAST Products Product specification
FAST 74F807
Octal shift/count registered transceiver with adder and parity (3–State)
June 18, 1991
2

INPUT AND OUTPUT LOADING AND FAN OUT TABLE

PINS DESCRIPTION
74F (U.L.) HIGH/LOW LOAD VALUE HIGH/LOW
An, Bn Data I/O inputs 3.5/0.166
70µA/70µA
OEA, OEB A output enable inputs 1.0/0.033
20µA/20µA
CI/SI/CE Carry in/serial in/clock enable input 1.0/0.033
20µA/20µA
CP Clock input 1.0/0.033
20µA/20µA
MR Master reset input (active low) 1.0/0.033
20µA/20µA
Sn Select inputs 1.0/0.033
20µA/20µA
STATOUT Status out output 150/40 3mA/24mA
An, Bn Data I/O outputs 150/40 3mA/24mA
Note to input and output loading and fan out table
1. One (1.0) FAST unit load is defined as: 20
µA in the high state and 0.6mA in the low state.

PIN CONFIGURATION PIN CONFIGURATION PLCC

1 2 3 4 5 6 7 8 9
10 19
20
21
22
23
24
25
26
27
28
OEA OEB
A0 A1 A2
A3 GND GND
A4
A5
A6
A7
CI/SI/CE
CP
4 3 2 1 28 27
25 24 23 22 21 20
11
10
9
8
7
6
18
16 17151413
26
19
12
5
PLCC
A2
A3 GND GND
A4
A5
A6
11 12 13 14 15
16
17
18
V
CC
OEAA0A1 MR
STAT OUT
B0
B7
S2CPCI/
SI/
CE
A7
MR STATOUT B0 B1 B2 B3
B4 B5 B6 B7 S0 S1 S2
OEB
S1 S0
B1 B2 B3
V
CC
B4 B5 B6

LOGIC SYMBOL IEC/IEEE SYMBOL

2
1
EN3
3 4 5 8 9 10 11 13
13 17 16 15 14 28 1 2
26 25 24 23 21 20 19 18
R EN1 EN2
0
3
M
1
15
27
STATUS
OUT
OEA OEB CI/SI/CE MR
VCC = Pin 22 GND = Pin 7, 8
3 4 5 6 9 10 11 12
26 25 24 23 22 20 19 18
1
2 13 28
STATOUT 27
B0 B1 B2 B3 B4 B5 B6 B7
A0 A1 A2 A3 A4 A5 A6 A7
Philips Semiconductors FAST Products Product specification
FAST 74F807
Octal shift/count registered transceiver with adder and parity (3–State)
June 18, 1991
3

LOGIC DIAGRAM

Qn
SHIFTOUT
OEA
OEB
CP
MR
CI/SI/CE
S0
V
CC =
Pin 22,
GND = Pin 7, 8
1
2
14
28
13
17
LE
An
QIN
CIN
ADDER
SUMn
COUT
8 8 8 8
LE
Dn
DATA
REGISTERS
CP
TC
R
TCIN
TC
REGISTER
CP
QIN P0
PARITY
QIN An Bn SUMn CI/SI/CE
2 – 7,
9 – 12
26 –23, 21 – 18
27
8
8
8
8
RCOUT
R E G
I S T E R
C O N T R O L
STATOUT
A0 – A7
B0 – B7
16
15
S1
S2
HOLD
LOAD A
LOAD B
CNTE
CNTNE
CNT
SHIFT
ADD
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