Philips 74f569 DATASHEETS

INTEGRATED CIRCUITS

74F569

4-bit bidirectional binary synchronous counter (3-State)

Product specification 1996 Jan 05 IC15 Data Handbook

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Philips Semiconductors Product specification

74F5694-bit bidirectional binary synchronous counter (3-State)

FEA TURES

•4-bit bidirectional counting – binary counter

•Synchronous counting and loading

•Look ahead carry capability for easy cascading

•Preset capability for programmable operation

•Master Reset (MR) overrides all other inputs

•Synchronous Reset (SR) overrides counting and parallel loading

•Clock Carry (CC) output to be used as a clock for flip-flops,

•3-State outputs for bus organized systems

DESCRIPTION

The 74F569 is a fully synchronous Up/Down binary counter. It features preset capabilities for programmable operation, carry look ahead for programmable operation, carry look ahead for easy cascading, and U/D maximum flexibility there are both Synchronous and Master Reset inputs as well as both Clocked Carry (CC outputs. All state changes except Master Reset are initiated by rising edge of the clock. A High signal on the Output Enable (OE) input forces the output buffers into the high impedance state but does not prevent counting, resetting or parallel loading.

input to control the direction of counting. For

) and Terminal Count (TC)

PIN CONFIGURATION

VCC

U/D

CEP

GND

1 2

6 7

20 19 18 17 16 15 14 138 12 1110

SF01072

TC CC OE Q0 Q1 Q2 Q3

CET PE

TYPICAL

TYPE TYPICAL f

MAX

SUPPLY CURRENT

(TOTAL)

74F569 115MHz 40mA

ORDERING INFORMATION

ORDER CODE

DESCRIPTION

COMMERCIAL RANGE

VCC = 5V ±10%,

= 0°C to +70°C

amb

20-pin plastic DIP N74F569N SOT146-1

20-pin plastic SO N74F569D SOT163-1

PKG.

DWG. #

LOGIC SYMBOL

1 2 7

= Pin 20

GND = Pin 10

PE U/D

CP CEP CET MR SR OE

3456

0D1D2D3

Q0Q1Q2Q

13141516

CC TC

18 19

SF01056

LOGIC SYMBOL (IEEE/IEC)

17 1

12 7

9 11

3 4

5 6

CTR DIV 10

EN10 M1[UP] M2[DOWN]

C5/1,4,7,8+/2,4,7,8– Z6 G7

G8 5CT=0 M3[LOAD] M4[COUNT] CT=0

3,5D

1,7(CT=15)G9

6,7,8,9

2,7(CT=0)G9

18 19

16 15

14 13

SF01057

1996 Jan 05 853–0376 16193

Philips Semiconductors Product specification

74F5694-bit bidirectional binary synchronous counter (3-State)

INPUT AND OUTPUT LOADING AND FAN-OUT TABLE

PINS DESCRIPTION

D0 - D3 Parallel data inputs 1.0/1.0 20µA/0.6mA CEP Count Enable parallel input (active Low) 1.0/1.0 20µA/0.6mA CET Count Enable Trickle input (active Low) 1.0/2.0 20µA/1.2mA CP Clock input (active rising edge) 1.0/1.0 20µA/0.6mA PE Parallel Enable input (active Low) 1.0/2.0 20µA/1.2mA U/D Up/Down count control input 1.0/1.0 20µA/0.6mA OE Output Enable input 1.0/1.0 20µA/0.6mA MR Master Reset input (active Low) 1.0/1.0 20µA/0.6mA SR Synchronous Reset (active Low) 1.0/1.0 20µA/0.6mA TC Terminal count output (active Low) 50/33 1.0mA/20mA CC Clocked carry output (active Low) 50/33 1.0mA/20mA Q0 - Q3 Data outputs 150/40 3.0mA/24mA

NOTE: One (1.0) FAST Unit Load (U.L.) is defined as: 20µA in the High state and 0.6mA in the Low state.

74F(U.L.)

HIGH/LOW

LOAD VALUE

HIGH/LOW

FUNCTIONAL DESCRIPTION

The 74F569 counts in the modulo-16 binary sequence. From state 0 (LLLL) it will increment to 15 in the up mode; in the down mode it will decrement from 15 to 0. The clock inputs of all flip-flops are driven parallel through a clock buffer. All state changes (except due to Master Reset) occur synchronously with the Low-to-High transition of the Clock Pulse (CP

The circuit has five fundamental modes of operation, in order of precedence: asynchronous reset, synchronous reset, parallel load, count and hold. Six control inputs–Master Reset (MR Reset (SR Count Enable Parallel (CEP determine the mode of operation, as shown in the Function Table.

A Low signal on MR forces the flip-flop Q outputs Low. A Low signal on SR counting and parallel loading and allows the Q output to go Low on the next rising edge of CP. A Low signal on PE and allows information on the parallel data (Dn) inputs to be loaded into the flip-flops on the next rising edge of CP. With MR PE Conversely, a High signal on either CEP

The 74F569 uses edge-triggered flip-flops and changing the SR, PE, CEP cause errors, provided that the recommended setup and hold times, with respect to the rising edge of CP, are observed. Two types of outputs are provided as overflow/underflow indicators. The Terminal Count (TC Low, when the counter reaches zero in the down mode, or reaches maximum 15 in the up mode

TC presetting, or until U/D

), Count Enable Trickle (CET), Parallel Enable (PE),

overrides all other inputs and asynchronously

High, CEP and CET permit counting when both are Low.

, CET or U/D inputs when the CP is in either state does not

) output is normally High and goes Low provided CET is

will then remain Low until a state change occurs by counting or

or CET is changed.

) input.

), Synchronous

), and the Up/Down (U/D) input –

overrides

overrides counting

, SR, and

and CET inhibits counting.

To implement synchronous multistage counters, the connections between the TC output and the CEP and CET inputs can provide either slow or fast carry propagation. Figure 1 shows the connections for a simple ripple carry, in which the clock period must be longer than the CP to TC cumulative CET CET

to CP setup time of the last stage. This total delay plus setup time sets the upper limit on clock frequency. For faster clock rates, the carry look ahead connections in Figure 2 are recommended. In this scheme the ripple delay through the intermediate stages commences with the same clock that causes the first stage to tick over from Max to Min in the up mode, or Min to Max in the down mode, to start its final cycle. Since this takes 16 clocks to complete, there is plenty of time for the ripple to progress through the intermediate stages. The critical timing that limits the clock period is the CP to TC of the last stage. The TC internal race conditions and is therefore not recommended for use as a clock or asynchronous reset for flip-flops, register or counters.

For such applications, the Clocked Carry (CC The CC the CC

output will go Low, when the clock next goes Low and will stay Low until the clock goes High again; as shown in the CC Function Table. When the Output Enable (OE) is Low, the parallel data outputs Q0–Q3 are active and follow the flip-flop Q outputs. A High signal on OE does not prevent counting, loading or resetting.

LOGIC EQUATIONS: Count Enable=CEP Up: TC

=Q0×Q1×Q2×Q3×(Up)×CET Down: TC=Q0×Q1×Q2×Q3×(Down)×CET

to TC delays of the intermediate stages, plus the

delay of the first stage plus the CEP to CP setup time

output is normally High. When CEP, CET, and TC are Low,

forces Q0–Q3 to the High impedance state but

×CET×PE

delay of the first stage, plus the

output is subject to decoding spikes due to

) output is provided.

1996 Jan 05

Philips Semiconductors Product specification

OPERATING MODE

Hold (do nothing)

74F5694-bit bidirectional binary synchronous counter (3-State)

COUNT

CP TO ALL STAGES

COUNT

CP TO ALL STAGES

CET

STATE DIAGRAM

01234

LOW

COUNT DOWN COUNT UP

CET TC CET TC CET TC CET TC

SF01059

Figure 1. Multistage Counter with Ripple Carry

CEP

CET TC

CEP

CET TC

CEP

CET TC

CEP

CET

SF01061

Figure 2. Multistage Counter with Look-Ahead Carry

CC FUNCTION TABLE

INPUTS OUTPUT

SR PE CEP CET TC* CP CC

89101112

SF01058

L X X X X X H X L X X X X H X X H X X X H X X X H X X H X X X X H X H H H L L L

*=TC is generated internally H = High voltage level L = Low voltage level X = Don’t care

= Low Pulse

FUNCTION TABLE

H = High voltage level h = High voltage level one setup time prior to the Low-to-High clock transition L = Low voltage level l = Low voltage level one setup time prior to the Low-to-High clock transition X = Don’t care ↑ = Low-to-High clock transition

1996 Jan 05

INPUTS

MR SR PE CEP CET U/D CP

L X X X X X X Asynchronous reset h l X X X X

h h l X X X h h h l l h h h h l l l h H H H X X h H H X H X

↑ Synchronous reset ↑ ↑ ↑

Parallel load Count Up (increment)

Count Down (decrement) X X

Philips Semiconductors Product specification

74F5694-bit bidirectional binary synchronous counter (3-State)

LOGIC DIAGRAM

DCPQ

VCC= Pin 20 GND = Pin 10

1996 Jan 05

CEP CET

U/D

SF01062

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