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INTEGRATED CIRCUITS
74F564
Octal D flip-flop (3-State)
Product specification 1996 Jan 05
IC15 Data Handbook
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Philips Semiconductors Product specification
74F564Octal D flip-flop (3-State)
FEA TURES
•74F564 is broadside pinout version of 74F534
•Inputs and Outputs on opposite side of package allow easy
interface to Microprocessors
•Useful as an Input or Ouput port for Microprocessors
•3-State Ouputs for Bus interfacing
•Common Output Enable
•74F574 is a non-inverting version of 74F564
DESCRIPTION
The 74F564 has a broadside pinout configuration to facilitate PC
board layout and allows easy interface with microprocessors.
It is an 8-bit, edge triggered register coupled to eight 3-State output
buffers. The two sections of the device are controlled independently
by the clock (CP) and Output Enable (OE
The register is fully edge-triggered. The state of each D input, one
setup time before the Low-to-High clock transition is transferred to
the corresponding flip-flop’s Q
output.
The 3-State output buffers are designed to drive heavily loaded
3-State buses, MOS memories, or MOS microprocessors. The
active Low Output Enable (OE
) controls all eight 3-State buffers
independently of the register operation. When OE
register appears at the outputs. When OE
high impedance “off” state, which means they will neither drive nor
load the bus.
) control gates.
is Low, data in the
is High, the outputs are in
PIN CONFIGURATION
1
2
D0
3
D1
4
D2
5
D3
6
D4
7
D5
8
D6
9
D7
10 11
GND
TYPE TYPICAL f
MAX
74F564 180MHz 50mA
20OE
V
CC
Q0
19
18
1
Q
17
Q
2
16
Q
3
15
Q
4
14
5
Q
13
Q
6
12
Q
7
CP
SF01052
TYPICAL SUPPL Y
CURRENT
(TOTAL)
ORDERING INFORMATION
COMMERCIAL RANGE
DESCRIPTION
VCC = 5V ±10%,
T
= 0°C to +70°C
amb
20-Pin Plastic DIP N74F564N SOT146-1
20-Pin Plastic SOL N74F564D SOT163-1
PKG.
DWG #
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
PINS DESCRIPTION
74F (U.L.)
HIGH/LOW
D0 - D7 Data inputs 1.0/1.0 20µA/0.6mA
OE Output Enable input (active Low) 1.0/1.0 20µA/0.6mA
CP Clock Pulse input (active rising edge) 1.0/1.0 20µA/0.6mA
Q0 - Q7 3-State outputs 150/40 3.0mA/24mA
NOTE: One (1.0) FAST Unit Load (U.L.) is defined as: 20µA in the High state and 0.6mA in the Low state.
LOGIC SYMBOL
2
D0 D1Q1D2
11 CP
1
OE
Q0
VCC=Pin 20
GND=Pin 10
345678
D5
Q2 Q3D3Q4D4Q5
Q6D6Q7
141516171819
SF01053
9
D7
1213
LOGIC SYMBOL (IEEE/IEC)
1
11
2
3
4
5
6
7
8
9
EN1
C2
2D
1
LOAD VALUE
HIGH/LOW
19
18
17
16
15
14
13
12
SF01054
1996 Jan 05 853-0166 16189
2
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Philips Semiconductors Product specification
74F564Octal D flip-flop (3-State)
LOGIC DIAGRAM
D0 D1 D2 D3 D4 D5 D6 D7
23456789
D
CP
OE
VCC=Pin 20
GND=Pin 10
CPDQ CPDQ CP Q
11
1
0Q1Q2Q3Q4Q5Q6Q7
Q
CPDQ CPDQ CPDQ CPDQ CPDQ
FUNCTION TABLE
INPUTS
OE CP Dn
L
L
↑
↑
l
h
INTERNAL
REGISTER
L
H
L ↑ X NC NC Hold
H
H
↑
↑
Dn
X
NC
Dn
H = High voltage level
h = High voltage level one setup time prior to the Low-to-High clock transition
L = Low voltage level
l = Low voltage level one setup time prior to the Low-to-High clock transition
NC= No change
X = Don’t care
Z = High impedance “off” state
↑ = Low-to-High clock transition
= Not a Low-to-High clock transition
↑
OUTPUTS
Q0 – Q7
H
L
Z
Z
1213141516171819
SF01055
Load and read register
Disable outputs
ABSOLUTE MAXIMUM RATINGS
(Operation beyond the limits set forth in this table may impair the useful life of the device.
Unless otherwise noted these limits are over the operating free-air temperature range.)
SYMBOL
V
CC
V
IN
I
IN
V
OUT
I
OUT
T
amb
T
stg
1996 Jan 05
Supply voltage –0.5 to +7.0 V
Input voltage –0.5 to +7.0 V
Input current –30 to +5.0 mA
Voltage applied to output in High output state –0.5 to +V
Current applied to output in Low output state 48 mA
Operating free-air temperature range 0 to +70 °C
Storage temperature –65 to +150 °C
PARAMETER RATING UNIT
3
CC
V