Philips 74f534 DATASHEETS
INTEGRATED CIRCUITS
74F534
Octal D flip-flop, inverting (3-State)
Product specification
Supersedes data of 1999 Jan 08
IC15 Data Handbook
2000 Aug 01
Philips Semiconductors Product specification
74F534Octal D flip-flop, inverting (3-State)
FEA TURES
•8-bit positive edge-triggered register
•3-State inverting output buffers
•Common 3-State Output register
•Independent register and 3-State buffer operation
DESCRIPTION
active Low Output Enable (OE
independent of the latch operation. When OE
transparent data appears at the outputs. When OE
outputs are in high impedance “off” state, which means they will
neither drive nor load the bus.
TYPE
TYPICAL f
74F534 165MHz 51mA
) controls all eight 3-State buffers
is Low, the latched or
is High, the
TYPICAL SUPPL Y
MAX
CURRENT
(TOTAL)
The 74F534 is an 8-bit edge-triggered register coupled to eight
3-State output buffers. The two sections of the device are controlled
independently by the Clock (CP) and Output Enable (OE) control
gates.
The register is fully edge-triggered. The state of each D input, one
setup time before the Low-to-High clock transition is transferred to
the corresponding flip-flop’s Q
output.
The 3-State output buffers are designed to drive heavily loaded
3-State buses, MOS memories, or MOS microprocessors. The
ORDERING INFORMATION
COMMERCIAL
DESCRIPTION
20-Pin Plastic DIP N74F534N SOT146-1
20-Pin Plastic SOL N74F534D SOT163-1
RANGE
V
= 5V ±10%,
CC
T
= 0°C to +70°C
amb
PKG DWG #
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
PINS DESCRIPTION
74F (U.L.)
HIGH/LOW
D0 - D7 Data inputs 1.0/1.0 20µA/0.6mA
OE Output Enable input (active Low) 1.0/1.0 20µA/0.6mA
CP Clock Pulse input (active rising edge) 1.0/1.0 20µA/0.6mA
Q0 - Q7 Data outputs 150/40 3.0mA/24mA
NOTE: One (1.0) FAST Unit Load (U.L.) is defined as: 20µA in the High state and 0.6mA in the Low state.
LOAD VALUE
HIGH/LOW
PIN CONFIGURATION
1
OE
2
Q0
3
D0
4
D1
5
Q
1
6
2
Q
7
D2
8
D3
9
Q
3Q4
10 11
GND
20
19
18
17
16
15
14
13
12
SF00982
V
Q
D7
D6
Q
Q
D5
D4
CP
CC
7
6
5
LOGIC SYMBOL
34781314
D0 D1Q1D2
11 CP
1
OE
Q0
VCC=Pin 20
GND=Pin 10
Q2Q3D3Q4D4Q5
D5
15129652
17 18
D7
Q6D6Q7
1916
SF00984
2000 Aug 01 853-0374 24250
2
Philips Semiconductors Product specification
OPERATING MODES
74F534Octal D flip-flop, inverting (3-State)
LOGIC SYMBOL (IEEE/IEC)
1
11
3
4
7
8
13
14
17
18
LOGIC DIAGRAM
D0 D1 D2 D3 D4 D5 D6 D7
11
CP
EN1
C1
2D
3 4 7 8 13 14 17 18
CPDQ CPDQ CP Q
1
2
5
6
9
12
15
16
19
SF00986
D
CPDQ CPDQ CPDQ CPDQ CPDQ
1
OE
VCC=Pin 20
GND=Pin 10
0Q1Q2Q3Q4Q5Q6Q7
Q
FUNCTION TABLE
INPUTS
OE CP Dn
L
L
↑
↑
l
h
INTERNAL
REGISTER
L
H
L ↑ X NC NC Hold
H
H
↑
↑
Dn
X
NC
Dn
H = High voltage level
h = High voltage level one setup time prior to the Low-to-High clock transition
L = Low voltage level
l = Low voltage level one setup time prior to the Low-to-High clock transition
NC= No change
X = Don’t care
Z = High impedance “off” state
↑ = Low-to-High clock transition
= Not a Low-to-High clock transition
↑
OUTPUTS
Q0 – Q7
H
L
Z
Z
191615129652
SF00988
Load and read register
Disable outputs
2000 Aug 01
3
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