Philips 74f5074 DATASHEETS
INTEGRATED CIRCUITS
74F5074
Synchronizing dual D-type flip-flop/clock
driver
Product specification
IC15 Data Handbook
1990 Sep 14
Philips Semiconductors Product specification
74F5074Synchronizing dual D-type flip-flop/clock driver
FEA TURES
•Metastable immune characteristics
•Output skew guaranteed less than 1.5ns
•High source current (I
applications
= 15mA) ideal for clock driver
OH
•Pin out compatible with 74F74
•74F50728 for synchronizing cascaded D–type flip–flop
•See 74F50729 for synchronizing dual D–type flip–flop with
edge–triggered set and reset
•See 74F50109 for synchronizing dual J–K positive
edge–triggered flip–flop
•Industrial temperature range available (–40°C to +85°C)
TYPE
TYPICAL f
max
74F5074 120MHz 20mA
ORDERING INFORMATION
ORDER CODE
DESCRIPTION COMMERCIAL RANGE PKG DWG #
VCC = 5V ±10%,
T
= 0°C to +70°C
amb
14–pin plastic DIP N74F5074N SOT27-1
14–pin plastic SO N74F5074D SOT108-1
TYPICAL SUPPL Y
CURRENT (TOTAL)
PIN CONFIGURATION
1
R
D0
2
D0
3
CP0
4
SD0
Q0
5
0
Q
6
GND
IEC/IEEE SYMBOL
3
CP0
4
SD0
1
RD0
11
CP1
10
SD1
13
RD1
VCC = Pin 14
GND = Pin 7
SF00582
212
D1D0
Q0 Q0 Q1 Q1
56 98
SF00583
V
14
CC
13
D1
R
D1
12
11
CP1
10
SD1
9
Q1
87
Q1
INPUT AND OUTPUT LOADING AND FAN OUT TABLE
74F
PINS DESCRIPTION
(U.L.)
HIGH/
LOW
D0, D1 Data inputs 1.0/0.417 20µA/250µA
CP0, CP1
Clock inputs (active
rising edge)
1.0/1.0 20µA/20µA
SD0, SD1 Set inputs (active low) 1.0/1.0 20µA/20µA
RD0, RD1
Q0, Q1, Q0,
Q1
Reset inputs (active
low)
Data outputs
1.0/1.0 20µA/20µA
750/33
NOTE: One (1.0) FAST unit load is defined as: 20µA in the high
state and 0.6mA in the low state.
LOAD VAL-
UE HIGH/
LOW
15mA/20mA
LOGIC SYMBOL
4
3
2
1
10
11
12
13
&
S
C1
1D
R
S
C2
2D
R
3
6
9
8
SF00584
September 14, 1990 853-1391 00419
2
Philips Semiconductors Product specification
74F5074Synchronizing dual D-type flip-flop/clock driver
LOGIC DIAGRAM
4, 10
SD
D
R
CP
D
VCC = Pin 14
GND = Pin 7
1, 13
3, 11
2, 12
5, 9
6, 8
SF00585
Q
Q
DESCRIPTION
The 74F5074 is a dual positive edge–triggered D–type featuring
individual data, clock, set and reset inputs; also true and
complementary outputs.
Set (S
Dn) and reset (RDn) are asynchronous active low inputs and
operate independently of the clock (CPn) input. Data must be stable
just one setup time prior to the low–to–high transition of the clock for
guaranteed propagation delays.
Clock triggering occurs at a voltage level and is not directly related
to the transition time of the positive–going pulse. Following the hold
time interval, data at the Dn input may be changed without affecting
the levels of the output.
The 74F5074 is designed so that the outputs can never display a
metastable state due to setup and hold time violations. If setup time
and hold time are violated the propagation delays may be extended
beyond the specifications but the outputs will not glitch or display a
metastable state. Typical metastability parameters for the 74F5074
are: τ ≅ 135ps and T
≅ 9.8 X 10
o
6
sec where τ represents a
function of the rate at which a latch in a metastable state resolves
that condition and T
represents a function of the measurement of
0
the propensity of a latch to enter a metastable state.
Metastable Immune Characteristics
Philips Semiconductor uses the term ’metastable immune’ to
describe characteristics of some of the products in its family.
Specifically the 74F50XXX family presently consist of 4 products
which will not glitch or display an output anomaly under any
circumstances including setup and hold time violations. This claim is
easily verified on the 74F5074. By running two independent signal
generators (see Fig. 1) at nearly the same frequency (in this case
10MHz clock and 10.02 MHz data) the device–under–test can be
often be driven into a metastable state. If the Q output is then used
to trigger a digital scope set to infinite persistence the Q
build a waveform. An experiment was run by continuously operating
the devices in the region where metastability will occur.
output will
When the device–under–test is a 74F74 (which was not designed
with metastable immune characteristics) the waveform will appear
as in Fig. 2.
Figure 2 shows clearly that the Q
output can vary in time with
respect to the Q trigger point. This also implies that the Q or Q
output waveshapes may be distorted. This can be verified on an
analog scope with a charge plate CRT. Perhaps of even greater
interest are the dots running along the 3.5V volt line in the upper
right hand quadrant. These show that the Q
output did not change
state even though the Q output glitched to at least 1.5 volts, the
trigger point of the scope.
When the device–under–test is a metastable immune part, such as
the 74F5074, the waveform will appear as in Fig. 3. The 74F5074 Q
output will appear as in Fig. 3. The 74F5074 Q output will not vary
with respect to the Q trigger point even when the a part is driven into
a metastable state. Any tendency towards internal metastability is
resolved by Philips Semiconductor patented circuitry. If a metastable
event occurs within the flop the only outward manifestation of the
event will be an increased clock–to–Q/Q
propagation delay. This
propagation delay is, of course, a function of the metastability
characteristics of the part defined by τ and T
0.
The metastability characteristics of the 74F5074 and related part
types represent state–of–the–art TTL technology.
After determining the T
and t of the flop, calculating the mean time
0
between failures (MTBF) is simple. Suppose a designer wants to
use the 74F5074 for synchronizing asynchronous data that is
arriving at 10MHz (as measured by a frequency counter), has a
clock frequency of 50MHz, and has decided that he would like to
sample the output of the 74F5074 10 nanoseconds after the clock
edge. He simply plugs his number into the equation below:
MTBF = e
(t’/t)
/ TofCf
I
In this formula, fC is the frequency of the clock, fI is the average
input event frequency , and t’ is the time after the clock pulse that the
output is sampled (t’ < h, h being the normal propagation delay). In
this situation the f
because input events consist of both of low and high transitions.
Multiplying f
clear that the MTBF is greater than 10
formula the actual MTBF is 1.51 X 10
SIGNAL GENERATOR
SIGNAL GENERATOR
will be twice the data frequency of 20 MHz
I
15
by fC gives an answer of 10
I
Hz2. From Fig. 4 it is
10
seconds. Using the above
10
seconds or about 480 years.
DQ
Q
CP
TRIGGER
DIGITAL
SCOPE
INPUT
SF00586
Figure 1. Test Set-up
September 14, 1990
3
Philips Semiconductors Product specification
74F5074Synchronizing dual D-type flip-flop/clock driver
COMP ARISON OF METASTABLE IMMUNE AND NON–IMMUNE CHARACTERISTICS
4
3
2
1
0
Time base = 2.00ns/div Trigger level = 1.5 Volts Trigger slope = positive
Figure 2. 74F74 Q Output triggered by Q output, set-up and hold times violated
3
2
1
0
Time base = 2.00ns/div Trigger level = 1.5 Volts Trigger slope = positive
Figure 3. 74F74 Q Output triggered by Q output, set-up and hold times violated
SF00587
SF00588
September 14, 1990
4
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