Philips 74f50109 DATASHEETS

INTEGRATED CIRCUITS

74F50109

Synchronizing dual J-K

positive edge-triggered flip-flop with metastable immune characteristics

Product specification IC15 Data Handbook

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1990 Sep 14

Philips Semiconductors Product specification

Synchronizing dual J–K

positive edge-triggered

flip-flop with metastable immune characteristics

FEA TURE

•Metastable immune characteristics

•Output skew guaranteed less than 1.5ns

•High source current (I

applications

= 15mA) ideal for clock driver

•Pinout compatible with 74F109

•See 74F5074 for synchronizing dual D-type flip-flop

•See 74F50728 for synchronizing cascaded D-type flip-flop

•See 74F50729 for synchronizing dual D-type flip-flop with

edge-triggered set and reset

TYPE

TYPICAL f

max

74F50109 150MHz 22mA

ORDERING INFORMATION

ORDER CODE

COMMERCIAL RANGE

DESCRIPTION

16–pin plastic DIP N74F50109N SOT38-4 16–pin plastic SO N74F50109D SOT109-1

VCC = 5V ±10%,

= 0°C to +70°C

amb

TYPICAL SUPPL Y

CURRENT( TOTAL)

PKG DWG #

PIN CONFIGURATION

LOGIC SYMBOL

74F50109

2 3

CP0

4 5

GND

2 14 3 13

CP0

SD0

RD0

CP1

SD1

RD1

Q0 Q0 Q1 Q1

13 12

CP1

SD1 Q1

107

SF00598

INPUT AND OUTPUT LOADING AND FAN OUT TABLE

74F (U.L.)

PINS DESCRIPTION

HIGH/

LOW

J0, J1 J inputs 1.0/0.417 20µA/250µA

K0, K1 K inputs 1.0/0.417 20µA/250µA

CP0, CP1

SD0, SD1

RD0, RD1

Clock inputs (active rising edge)

Set inputs (active low)

Reset inputs (active low)

1.0/0.033 20µA/20µA

Q0, Q1, Q0, Q1 Data outputs 750/33 15mA/20mA

NOTE: One (1.0) FAST unit load is defined as: 20µA in the high state and 0.6mA in the low state.

LOAD

VALUE

HIGH/LOW

VCC = Pin 16 GND = Pin 8

IEC/IEEE SYMBOL

2 4 3 1 5

14 12 13 15 11

R S

2K R S

6 7 10 9

SF00599

SF00600

September 14, 1990 853-1388 00422

Philips Semiconductors Product specification

Synchronizing dual J–K

positive edge-triggered

flip-flop with metastable immune characteristics

LOGIC DIAGRAM

6, 107, 9

3, 13

2, 14

4, 12

5, 11

1, 15

VCC = Pin 16 GND = Pin 8

SF00601

DESCRIPTION

The 74F50109 is a dual positive edge-triggered JK-type flip-flop featuring individual J, K complementary outputs.

Set (S

D) and reset (RD) are asynchronous active low inputs and

operate independently of the clock (CP) input. The J and K

are edge–triggered inputs which control the state changes of the flip–flops as described in the function table. The J and K

inputs must be stable just one setup time prior to the low–to–high transition of the clock for guaranteed propagation delays. The JK

inputs together.

and K The 74F50109 is designed so that the outputs can never display a metastable state due to setup and hold time violations. If setup time and hold time are violated the propagation delays may be extended beyond the specifications but the outputs will not glitch or display a metastable state. Typical metastability parameters for the 74F50109 are: τ ≅ 135ps and τ ≅ 9.8 X 10 of the rate at which a latch in a metastable state resolves that condition and T propensity of a latch to enter a metastable state.

, clock, set, and reset inputs; also true and

design allows operation as a D flip–flop by tying J

sec where τ represents a function

represents a function of the measurement of the

device–under–test can be often be driven into a metastable state. If the Q output is then used to trigger a digital scope set to infinite persistence the Q run by continuously operating the devices in the region where metastability will occur.

When the device–under–test is a 74F74 (which was not designed with metastable immune characteristics) the waveform will appear as in Fig. 2.

Fig. 2 shows clearly that the Q to the Q trigger point. This also implies that the Q or Q waveshapes may be distorted. This can be verified on an analog scope with a charge plate CRT. Perhaps of even greater interest are the dots running along the 3.5V volt line in the upper right hand quadrant. These show that the Q though the Q output glitched to at least 1.5 volts, the trigger point of the scope.

When the device–under–test is a metastable immune part, such as the 74F5074, the waveform will appear as in Fig. 3. The 74F5074 Q output will appear as in Fig. 3. The 74F5074 Q output will not vary with respect to the Q trigger point even when the a part is driven into a metastable state. Any tendency towards internal metastability is resolved by Philips Semiconductors patented circuitry. If a metastable event occurs within the flop the only outward manifestation of the event will be an increased clock–to–Q/Q propagation delay. This propagation delay is, of course, a function of the metastability characteristics of the part defined by τ and T

The metastability characteristics of the 74F5074 and related part types represent state–of–the–art TTL technology.

After determining the T between failures (MTBF) is simple. Suppose a designer wants to use the 74F50729 for synchronizing asynchronous data that is arriving at 10MHz (as measured by a frequency counter), has a clock frequency of 50MHz, and has decided that he would like to sample the output of the 74F50109 10 nanoseconds after the clock edge. He simply plugs his number into the equation below:

MTBF = e In this formula, fC is the frequency of the clock, fI is the average

input event frequency , and t’ is the time after the clock pulse that the output is sampled (t’ < h, h being the normal propagation delay). In this situation the fI will be twice the data frequency of 20 MHz because input events consist of both of low and high transitions. Multiplying f clear that the MTBF is greater than 10 formula MTBF is 1.51 X 10

74F50109

output will build a waveform.0 An experiment was

output can vary in time with respect

output did not change state even

and t of the flop, calculating the mean time

(t’/t)

/ TofCf

by fC gives an answer of 10

seconds or about 480 years.

Hz2. From Fig. 4 it is

seconds. Using the above

output

MET ASTABLE IMMUNE CHARACTERISTICS

Philips Semiconductors uses the term ’metastable immune’ to describe characteristics of some of the products in its FAST family. Specifically the 74F50XXX family presently consist of 4 products which displays metastable immune characteristics. This term means that the outputs will not glitch or display an output anomaly under any circumstances including setup and hold time violations.

This claim is easily verified on the 74F5074. By running two independent signal generators (see Fig. 1) at nearly the same frequency (in this case 10MHz clock and 10.02 MHz data) the

September 14, 1990

SIGNAL GENERATOR

TRIGGER

DIGITAL

SCOPE

INPUT

SF00586

Figure 1. Test setup

Philips Semiconductors Product specification

Synchronizing dual J–K

positive edge-triggered

flip-flop with metastable immune characteristics

COMP ARISON OF METASTABLE IMMUNE AND NON–IMMUNE CHARACTERISTICS

Time base = 2.00ns/div Trigger level = 1.5 Volts Trigger slope = positive

Figure 2. 74F74 Q output triggered by Q output, Setup and Hold times violated

74F50109

SF00602

Time base = 2.00ns/div Trigger level = 1.5 Volts Trigger slope = positive

Figure 3. 74F74 Q output triggered by Q output, Setup and Hold times violated

SF00588

September 14, 1990

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