Philips 74f395 DATASHEETS

Philips Semiconductors Product specification

74F3954-bit cascadable shift register (3-State)

1

1990 Oct 23 853–0370 00780

FEATURES

•4-bit parallel load shift register

•Independent 3-State buffer outputs, Q0–Q3

•Separate Qs output for serial expansion

•Asynchronous Master Reset

DESCRIPTION

The 74F395 is a 4-bit Shift Register with serial and parallel
synchronous operating modes and 3-State buffer outputs. The
shifting and loading operations are controlled by the state of the
Parallel Enable (PE) input. When PE is High, data is loaded from the
Parallel Data inputs (D0–D3) into the register synchronous with the
High-to-Low transition of the Clock input (CP). When PE is Low, the
data at the Serial Data input (Ds) is loaded into the Q0 flip-flop, and
the data in the register is shifted one bit to the right in the direction
(Q0Q1Q2Q3) synchronous with the negative clock transition.
The PE and Data inputs are fully edge-triggered and must be stable
one setup prior to the High-to-Low transition of the clock.

The Master Reset (MR

) is an asynchronous active-Low input. When

Low, the MR

overrides the clock and all other inputs and clears the

register.
The 3-state output buffers are designed to drive heavily loaded

3-State buses, or large capacitive loads.
The active-Low Output Enable (OE

) controls all four 3-State buffers
independent of the register operation. The data in the register
appears at the outputs when OE

is Low. The outputs are in High
impedance “OFF” state, which means they will neither drive nor load
the bus when OE

is High. The output from the last stage is brought
out separately. This output (Qs) is tied to the Serial Data input (Ds)
of the next register for serial expansion applications. The Qs output
is not affected by the 3-State buffer operation.

PIN CONFIGURATION

16
15
14
13
12
11
107

6

5

4

3

2

1

PE

V

CC

Q3
Qs
CP

Q2

Q0
Q1

MR

Ds

D3

D0
D1
D2

SF00940

98GND OE

TYPE TYPICAL f

MAX

TYPICAL SUPPL Y CURRENT

(TOTAL)

74F395 120MHz 32mA

ORDERING INFORMATION

DESCRIPTION

COMMERCIAL RANGE

V

CC

= 5V ±10%, T

amb

= 0°C to +70°C

16-pin plastic DIP N74F395N

16-pin plastic SO N74F395D

INPUT AND OUTPUT LOADING AND FAN-OUT TABLE

PINS DESCRIPTION

74F (U.L.)

HIGH/LOW

LOAD VALUE

HIGH/LOW

D0 – D3 Data inputs 1.0/1.0 20µA/0.6mA

Ds Serial data input 1.0/1.0 20µA/0.6mA

PE Parallel Enable input 1.0/1.0 20µA/0.6mA
MR Master Reset input (active Low) 1.0/1.0 20µA/0.6mA
OE Output Enable input (active Low) 1.0/1.0 20µA/0.6mA

CP Clock Pulse input (active falling edge) 1.0/1.0 20µA/0.6mA

Qs Serial expansion output 50/33 1.0mA/20mA

Q0–Q3 Data outputs (3-State) 150/40 3.0mA/24mA

NOTE:

One (1.0) FAST unit load is defined as: 20µA in the High state and 0.6mA in the Low state.

Philips Semiconductors Product specification

74F3954-bit cascadable shift register (3-State)

1990 Oct 23

2

LOGIC SYMBOL

10

7

PE
CP

15 14 13 12

Q0 Q1 Q2 Q3

1

9

OE
MR

SF00941

VCC= Pin 16
GND = Pin 8

3 4 5 6

D0 D1 D2 D3

2

Ds

11

Qs

IEC/IEEE SYMBOL (IEEE/IEC)

10

2,3D

SF00942

2

4
5
6

1,3D

R

M1[LOAD]

C3/2

1
9
7

SRG4

13
12
11

EN4

M2[SHIFT]

4

4

3

1,3D

15

14

LOGIC DIAGRAM

VCC = Pin 16
GND = Pin 8

SF00943

R

Q

CLR

CP

QS

R

Q

CLR

CP

QS

R

Q

CLR

CP

QS

R

Q

CLR

CP

QS

15

14

13

12

11

Q0

Q1

Q2

Q3

Qs

OE

CP

MR

PE

Ds

D0

D1

D2

D3

9

10

1

7

2

3

4

5

6

Philips Semiconductors Product specification

74F3954-bit cascadable shift register (3-State)

1990 Oct 23

3

MODE SELECT–FUNCTION TABLE

INPUTS OUTPUTS

REGISTER

MR CP PE Ds Dn Q0 Q1 Q2 Q3

OPERATING

MODES

L X X X X L L L L Reset (clear)

H

#

l l X L q0 q1 q2

H

#

l h X H q0 q1 q2

Shift right

H

#

h X l L L L L

H

#

h X h H H H H

Parallel load

INPUTS OUTPUTS

3-STATE BUFFER

OE Qn (Register) Q0, Q1, Q2, Q3 Qs

OPERATING

MODES

L L L L
L H H H

Read

H L Z L
H H Z H

Disable buffers

H = High voltage level
h = High voltage level one set-up time prior to the High-to-Low

clock transition
L = Low voltage level
l = Low voltage level one set-up time prior to the High-to-Low

clock transition
qn = Lower case letters indicate the state of the referenced input

(or output) one set-up time prior to the High-to-Low clock

transition
X = Don’t care
Z = High impedance “OFF” state
# = High-to-Low clock transition

ABSOLUTE MAXIMUM RATINGS

(Operation beyond the limits set forth in this table may impair the useful life of the device.
Unless otherwise noted these limits are over the operating free-air temperature range.)

SYMBOL

PARAMETER RATING UNIT

V

CC

Supply voltage –0.5 to +7.0 V

V

IN

Input voltage –0.5 to +7.0 V

I

IN

Input current –30 to +5 mA

V

OUT

Voltage applied to output in High output state –0.5 to +5.5 V

Qs 40 mA

I

OUT

Current applied to output in Low output state

Q0–Q3 48 mA

T

amb

Operating free-air temperature range 0 to +70 °C

T

stg

Storage temperature range –65 to +150 °C

RECOMMENDED OPERATING CONDITIONS

LIMITS

SYMBOL

PARAMETER

MIN NOM MAX

UNIT

V

CC

Supply voltage 4.5 5.0 5.5 V

V

IH

High-level input voltage 2.0 V

V

IL

Low-level input voltage 0.8 V

I

IK

Input clamp current –18 mA

Qs –1 mA

IOHHigh-level output current

Q0–Q3 –3 mA
Qs 20 mA

IOLLow-level output current

Q0–Q3 24 mA

T

amb

Operating free-air temperature range 0 70 °C