Philips 74f373, 74f374 DATASHEETS
FAST PRODUCTS
74F373
Octal transparent latch (3-State)
74F374
Octal D flip-flop (3-State)
Product specification 1994 Dec 05
IC15 Data Handbook
Philips Semiconductors
Philips Semiconductors Product specification
74F373/74F374Latch/flip-flop
74F373 Octal transparent latch (3-State)
74F374 Octal D-type flip-flop (3-State)
FEA TURES
•8-bit transparent latch — 74F373
•8-bit positive edge triggered register — 74F374
•3-State outputs glitch free during power-up and power-down
•Common 3-State output register
•Independent register and 3-State buffer operation
•SSOP Type II Package
DESCRIPTION
The 74F373 is an octal transparent latch coupled to eight 3-State
output devices. The two sections of the device are controlled
independently by enable (E) and output enable (OE
The data on the D inputs is transferred to the latch outputs when the
enable (E) input is high. The latch remains transparent to the data
input while E is high, and stores the data that is present one setup
time before the high-to-low enable transition.
The 3-State output buffers are designed to drive heavily loaded
3-State buses, MOS memories, or MOS microprocessors.
The active low output enable (OE
independent of the latch operation. When OE
transparent data appears at the output.
When OE
which means they will neither drive nor load the bus.
is high, the outputs are in high impedance “off” state,
) controls all eight 3-State buffers
) control gates.
is low, latched or
The 74F374 is an 8-bit edge triggered register coupled to eight
3-State output buffers. The two sections of the device are controlled
independently by clock (CP) and output enable (OE
The register is fully edge triggered. The state of the D input, one
setup time before the low-to-high clock transition is transferred to the
corresponding flip-flop’s Q output.
The 3-State output buffers are designed to drive heavily loaded
3-State buses, MOS memories, or MOS microprocessors.
The active low output enable (OE
independent of the register operation. When OE
the register appears at the outputs. When OE
are in high impedance “off” state, which means they will neither drive
nor load the bus.
TYPE
74F373 4.5ns 35mA
TYPE TYPICAL f
74F374 165MHz 55mA
PROPAGATION
) controls all eight 3-State buffers
TYPICAL
DELA Y
max
) control gates.
is low, the data in
is high, the outputs
TYPICAL SUPPL Y
CURRENT
(TOTAL)
TYPICAL SUPPL Y
CURRENT
(TOTAL)
ORDERING INFORMATION
ORDER CODE
DESCRIPTION COMMERCIAL RANGE PKG DWG #
VCC = 5V ±10%, T
20-pin plastic DIP N74F373N, N74F374N SOT146-1
20-pin plastic SOL N74F373D, N74F374D SOT163-1
20-pin plastic SSOP type II N74F373DB, N74374DB SOT399-1
= 0°C to +70°C
amb
INPUT AND OUTPUT LOADING AND FAN OUT TABLE
PINS DESCRIPTION
D0 - D7 Data inputs 1.0/1.0
E (74F373) Enable input (active high) 1.0/1.0
OE Output enable inputs (active low) 1.0/1.0
CP (74F374) Clock pulse input (active rising edge) 1.0/1.0
Q0 - Q7 3-State outputs 150/40 3.0mA/24mA
NOTE: One (1.0) FAST unit load is defined as: 20µA in the high state and 0.6mA in the low state.
74F (U.L.)
HIGH/LOW
LOAD VALUE
HIGH/LOW
20µA/0.6mA
20µA/0.6mA
20µA/0.6mA
20µA/0.6mA
December 5, 1994 853-0369 14383
2
Philips Semiconductors Product specification
74F373/74F374Latch/flip-flop
PIN CONFIGURATION – 74F373
OE
1
Q0
2
D0
3
D1
4
Q1
5
Q2
6
D2
7
D3
8
Q3
9
GND
10 11
LOGIC SYMBOL – 74F373
3 4 7 8 13 14 17 18
D0 D1 D2 D3 D4 D5 D6 D7
11
E
OE
1
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
PIN CONFIGURATION – 74F374
OE
V
20
CC
19
Q7
18
D7
17
D6
16
Q6
15
Q5
14
D5
13
D4
12
Q4
E
SF00250
1
Q0
2
D0
3
D1
4
Q1
5
Q2
6
D2
7
D3
8
Q3
9
GND
10 11
V
20
Q7
19
D7
18
D6
17
Q6
16
Q5
15
D5
14
D4
13
Q4
12
CP
SF00253
CC
IEC/IEE SYMBOL – 74F374
3 4 7 8 13 14 17 18
D0 D1 D2 D3 D4 D5 D6 D7
11
CP
OE
1
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
2 5 6 9 12 15 16 19
= Pin 20
V
CC
GND = Pin 10
IEC/IEEE SYMBOL – 74F373
1
11
3
4
7
8
13
14
17
18
EN1
EN2
2D
2 5 6 9 12 15 16 19
V
= Pin 20
CC
SF00251
GND = Pin 10
SF00254
IEC/IEEE SYMBOL – 74F374
1
11
SF00252
2
5
6
9
12
15
16
19
13
14
17
18
1
EN1
C2
3
4
7
8
2D
1
2
5
6
9
12
15
16
19
SF00255
December 5, 1994
3
Philips Semiconductors Product specification
OPERATING MODE
Enable and read register
Latch and read register
Disable outputs
74F373/74F374Latch/flip-flop
LOGIC DIAGRAM FOR 74F373
D0
3
D1
4
D2
7
D3
8
D4
13
D5
14
D6
17
D7
18
V
= Pin 20
CC
GND = Pin 10
E
OE
Q0
D
Q
E
2
D
Q
E
11
1
Q1
D
Q
E
5
Q2
D
Q
E
6
Q3
D
Q
E
9
Q4
LOGIC DIAGRAM FOR 74F374
VCC = Pin 20
GND = Pin 10
CP
OE
D0
3
D
CP
11
1
D1
4
Q0
D
CP
2
Q
D2
7
Q1
D
CP
5
Q
D3
8
Q2
D
CP
6
Q
D4
13
Q
9
Q3
D
CP
D5
Q
Q4
FUNCTION TABLE FOR 74F373
INPUTS
OE E Dn
INTERNAL
REGISTER
L H L L L
L H H H H
L ↓ l L L
L ↓ h H H
L L X NC NC Hold
H L X NC Z
H H Dn Dn Z
NOTES:
H = High-voltage level
h = High state must be present one setup time before the high-to-low enable transition
L = Low-voltage level
l = Low state must be present one setup time before the high-to-low enable transition
NC= No change
X = Don’t care
Z = High impedance “off” state
↓ = High-to-low enable transition
OUTPUTS
Q0 - Q7
D
Q
E
12
14
D
Q
CP
12
Q5
Q5
D
E
15
D6
17
D
CP
15
D
Q
Q
Q6
Q6
Q
E
16
D7
18
D
CP
16
19
Q7
SF00256
Q
19
Q7
SF00257
p
December 5, 1994
4
Loading...