Philips 74f322 DATASHEETS

Philips Semiconductors

Product specification

74F3228-bit serial/parallel register with sign extend (3-State)

1988 Apr 22 853-0366 93020

FEATURES

•Multiplexed parallel I/O ports

•Separate serial input and output

•Sign extend function

•3-State outputs for bus applications

•Direct Overriding Clear

DESCRIPTION

The 74F322 is an 8-bit shift register with provision for either serial or parallel loading and with 3-State parallel outputs plus a bi-state serial output. Parallel data inputs and outputs are multiplexed to minimize pin count. State changes are initiated by the rising edge of the clock. Four synchronous modes of operation are possible: hold (store), shift right with serial entry, shift right with sign extend, and parallel load. An asynchronous Master Reset (MR

) input overrides

clocked operation and clears the registers. The 74F322 contains eight D-type edge triggered flip-flops and the

interstage gating required to perform right shift and the intrastage gating necessary for hold and synchronous parallel load operations. A Low signal on RE

enables shifting or parallel loading, while a High

signal enables the hold mode. A High signal on S/P

enables shift right, while a Low signal disables the 3-State output buffers and enables parallel loading. In the shift right mode a High signal on SE enables serial entry from either D0 or D1, as determined by the S input. A Low signal on SE

enables shift right, but Q7 reloads its contents, thus performing the sign extend function. A High signal on OE

disables the 3-State output buffers, regardless of the other control inputs. In this condition the shifting and loading operations can still be performed.

PIN CONFIGURATION

20 19 18 17 16 15 14 13 12

10 11

S SE D1

I/O7

I/O5

I/O3

I/O1

I/O6

I/O4

I/O2

I/O0

S/P

GND

SF00874

TYPE TYPICAL f

MAX

TYPICAL

SUPPLY CURRENT

(TOTAL)

74F322 125MHz 60mA

ORDERING INFORMATION

ORDER CODE

DESCRIPTION

COMMERCIAL RANGE

VCC = 5V ±10%, T

amb

= 0°C to +70°C

20-pin plastic DIP N74F322N

20-pin plastic SOL N74F322D

INPUT AND OUTPUT LOADING AND FAN-OUT TABLE

PINS DESCRIPTION

74F(U.L.)

HIGH/LOW

LOAD VALUE

HIGH/LOW

D0, D1 Serial data inputs 1.0/1.0 20µA/0.6mA S Serial data select input 1.0/2.0 20µA/1.2mA SE Sign Extend input 1.0/3.0 20µA/1.8mA CP Clock Pulse input (Active rising edge) 1.0/1.0 20µA/0.6mA S/P Serial (High) or Parallel (Low) mode control input 1.0/1.0 20µA/0.6mA RE Register Enable input (Active Low) 1.0/1.0 20µA/0.6mA MR Asynchronous Master Reset input (Active Low) 1.0/1.0 20µA/0.6mA OE Output Enable input (Active Low) 1.0/1.0 20µA/0.6mA Q7 Bi-state serial output 50/33 1.0mA/20mA

Multiplexed parallel data inputs or 3.5/1.0 70µA/0.6mA

I/On

3-State parallel outputs 150/40 3.0mA/24mA

NOTE: One (1.0) FAST Unit Load (U.L.) is defined as: 20µA in the High State and 0.6mA in the Low state.

Philips Semiconductors Product specification

74F3228-bit serial/parallel register with sign extend (3-State)

1988 Apr 22

LOGIC SYMBOL

3 17

4 16 5 15 6 14 7 13

2 18 11

D0 D1

I/O0 I/O2 I/O4 I/O6I/O1 I/O3 I/O5 I/O7

S RE

S/P

CP OE

VCC = Pin 20 GND = Pin 10

SF00875

LOGIC SYMBOL (IEEE/IEC)

SF00876

2EN15

C6/1 →

SRG8

8, 4

, 1, 6D

2, 6D

12, 13

Z14

G3 3M1[SHIFT]

3M2[PAR LOAD]

2, 96D

8, 15

8, 5

, 1, 6D 8, 4, 1, 6D 2, 6D

7, 15

FUNCTION TABLE

INPUTS INPUTS

OPERATING

MR RE S/P SE S OE* CP I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 Q7

OPERATING

MODE

L L

H X

X H

X X

L L

X X

L L

LLClear

H L L X X X ↑ I0 I1 I2 I3 I4 I5 I6 I7 I7 Parallel load H

L L

H H

L H

L L

↑↑D0D1O0O0O1O1O2O2O3O3O4O4O5O5O6O6O6O6Shift right

H L H L X L ↑ O0 O0 O1 O2 O3 O4 O5 O6 O6 Sign extend H H X X X L X NC NC NC NC NC NC NC NC NC Hold X

L X

X X

↑

Z Z

ZZNCNC3-State

* = When the input is High, all I/O terminals are at the high impedance state, sequential operation or clearing of the register is not

affected. H = High voltage level L = Low voltage level NC = No change X = Don’t care Z = High impedance “off” state ↑ = Low-to-High clock transition I0–I7 = The level of the steady state input at the respective I/O terminal is loaded into the flip-flop while the flip-flop outputs (except Q7) are

isolated from the I/O terminal. D0–D7 = The level of the steady state inputs to the serial multiplexer input. O0–O7= The level of the respective Qn flip-flop prior to the last clock Low-to-High transition.

↑

= Not a Low-to-High clock transition

Philips Semiconductors Product specification

74F3228-bit serial/parallel register with sign extend (3-State)

1988 Apr 22

LOGIC DIAGRAM

I/O0

S/P

SF00877

= Pin 20

GND = Pin 10

I/O1

I/O2

CP Q

I/O3

I/O4

I/O5

I/O6

I/O7

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