Philips 74f280b DATASHEETS
INTEGRATED CIRCUITS
74F280B
9-bit odd/even parity generator/checker
Product specification
IC15 Data Handbook
1996 Mar 12
Philips Semiconductors Product specification
74F280B9-bit odd/even parity generator/checker
FEA TURES
PIN CONFIGURATION
•High-impedance NPN base inputs for reduced loading
(20µA in Low and High states)
•Buffered inputs — one normalized load
•Word length easily expanded by cascading
•Industrial temperature range available (–40°C to +85°C)
DESCRIPTION
The 74F280B is a 9-bit Parity Generator or Checker commonly used
to detect errors in high speed data transmission or data retrieval
systems. Both Even (∑
for generating or checking even or odd parity on up to 9 bits.
The Even (∑
inputs (I
) parity output is High when an even number of Data
E
- I8) are High. The Odd (∑O) parity output is High when an
0
odd number of Data inputs are High.
Expansion to larger word sizes is accomplished by tying the Even
(∑
) outputs of up to nine parallel devices to the data inputs of the
E
final stage. This expansion scheme allows an 81-bit data word to be
checked in less than 20ns.
ORDERING INFORMATION
DESCRIPTION
14-pin plastic DIP N74F280BN I74F280BN SOT27-1
14-pin plastic SO N74F280BD I74F280BD SOT108-1
) and Odd (∑O) parity outputs are available
E
COMMERCIAL RANGE
V
= 5V ±10%,
CC
= 0°C to +70°C
T
amb
TYPE
74F280B 5.5ns 26mA
INDUSTRIAL RANGE
V
= 5V ±10%,
CC
= –40°C to +85°C
T
amb
1
I
6
2
I
7
NC
3
4
I
8
Σ
5
E
Σ
6
O
GND
TYPICAL
PROPAGATION
DELAY
14
V
CC
13
I
5
12
I
4
11
I
3
10
I
2
9
I
1
87
I
0
SF00849
TYPICAL
SUPPLY CURRENT
(TOTAL)
PKG. DWG. #
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
PINS DESCRIPTION
I0 - I
∑E, ∑
8
O
Data inputs 1.0/0.033 20µA/20µA
Parity outputs 50/33 1.0mA/20mA
NOTE:
One (1.0) FAST Unit Load is defined as: 20µA in the High state and 0.6mA in the Low state.
LOGIC SYMBOL
8 9 10 11 12 13 1 2 4
I0I1I2I3I4I5I6I7I
Σ
Σ
E
56
O
SF00845
8
IEC/IEEE SYMBOL
VCC=Pin 14
GND=Pin 7
74F(U.L.)
HIGH/LOW
LOAD VALUE
HIGH/LOW
8
9
10
11
12
13
1
2
4
2K
Σ
E
Σ
O
5
6
SF00846
1996 Mar 12 853-0363 16555
2
Philips Semiconductors Product specification
74F280B9-bit odd/even parity generator/checker
LOGIC DIAGRAM
8
I
0
9
I
1
10
I
2
11
I
3
12
I
4
13
I
5
1
I
6
2
I
7
4
I
8
VCC=Pin 14
GND=Pin 7
FUNCTION TABLE
INPUTS OUTPUTS
Number of High Data Inputs (I0 - I8)
Even — 0, 2, 4, 6, 8 H L
Odd — 1, 3, 5, 7, 9 L H
H = High voltage level
L = Low voltage level
∑
E
5
Σ
E
6
Σ
O
SF00847
∑
O
1996 Mar 12
3
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