Philips 74f195a DATASHEETS

INTEGRATED CIRCUITS

74F195A

4-bit parallel-access shift register

Product specification
IC15 Data Handbook

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1996 Mar 12

Philips Semiconductors Product specification

D0–D3

Data inputs

J, K

J-K or D type serial inputs

CP

Clock Pulse input (active rising edge)

MR

Master Reset input (active Low)

74F195A4-bit parallel-access shift register

J, K

FEA TURES

•Shift right and parallel load capability

•J – K (D) inputs to first stage

•Complement output from last stage

•Asynchronous Master Reset

•Diode inputs

DESCRIPTION

The 74F195A is a 4-Bit Parallel Access Shift Register and its
functional characteristics are indicated in the Logic Diagram and
Function Table. This device is useful in a variety of shifting, counting
and storage applications. It performs serial, parallel, serial to
parallel, or parallel to serial data transfers at very high speeds.

The 74F195A operates in two primary modes: shift right (Q0→Q1)
and parallel load, which are controlled by the state of the Parallel
Enable (PE
and K
direction Q0→Q1→Q2→Q3 following each Low-to-High clock
transition.

The J and K
special applications, and by tying the two together the simple D-type
input is made for general applications.

The device appears as four common clocked D flip-flops when the
PE
parallel inputs (D0–D3) is transferred to the respective Q0–Q3
outputs. Shift left operation (Q3–Q2) can be achieved by tying the
Qn outputs to the Dn-1 inputs and holding the PE

All parallel and serial data transfers are synchronous, occurring after
each Low-to-High clock transition. The 74F195A utilizes
edge-triggering, therefore there is no restriction on the activity of the

) input. Serial data enters the first flip-flop (Q0) via the J

inputs when the PE input is High, and is shifted one bit in the

inputs provide the flexibility of the J-K type input for

input is Low. After the Low-to-High clock transition, data on the

input Low.

, Dn, and PE inputs for logic operation, other than the set-up and

hold time requirements.
A Low on the asynchronous Master Reset (MR

) input sets all Q

outputs Low, independent of any other input condition.

PIN CONFIGURATION

1

MR

2

J

3

K

D0

4

D1

5

D2

6

D3

TYPE TYPICAL f

MAX

74F195A 180MHz 40mA

16

V

CC

15

Q0

14

Q1

13

Q2

12

Q3

11

Q3

107

CP

98GND PE

SF00757

TYPICAL

SUPPLY CURRENT

(TOTAL)

ORDERING INFORMATION

COMMERCIAL RANGE

DESCRIPTION

16-pin plastic DIP N74F195AN SOT 38-4

16-pin plastic SO N74F195AD SOT 109-1

VCC = 5V ±10%,

T

= 0°C to +70°C

amb

PKG. DWG. #

INPUT AND OUTPUT LOADING AND FAN-OUT TABLE

PINS DESCRIPTION

Q0–Q3,

Q3

NOTE:

One (1.0) FAST unit load is defined as: 20µA in the High state and 0.6mA in the Low state.

1996 Mar 12 853-0024 16555

74F (U.L.)

LOAD VALUE HIGH/LOW

HIGH/LOW

p

p

p

p

p

74F195 1.0/0.033 20µA/20µA

74F195A 1.0/1.0 20µA/0.6mA

74F195 1.0/0.033 20µA/20µA

74F195A 1.0/1.0 20µA/0.6mA

74F195 1.0/0.033 20µA/20µA

74F195A 1.0/1.0 20µA/0.6mA

74F195 2.0/0.066 40µA/40µA

74F195A 1.0/1.0 20µA/0.6mA

Data outputs 50/33 1.0mA/20mA

2

Philips Semiconductors Product specification

74F195A4-bit parallel-access shift register

LOGIC SYMBOL

9
2

10

3
1MR

= Pin 16

V

CC

GND = Pin 8

PE
J
CP

K

LOGIC DIAGRAM

CP

PE

MR

IEC/IEEE SYMBOL

4

56

7

9

CP

R

1

10

2
3
4
5
6
7

R

D

Q2 Q3

13 12

D3D0

11Q3

SF00758

D1 D2

Q0 Q1

15 14

10

9

2

J

3

K

1

4

D0

M1
R

C2/1

1, 2J
1, 2K
1, 2D
1, 2D

S

SRG4

Q

Q

SF00759

15

15

14
13
12

11

Q0

VCC = Pin 16
GND = Pin 8

1996 Mar 12

5

D1

6

D2

7

D3

CP

R

CP

R

CP

R

R

D

R

D

R

D

S

Q

S

Q

S

Q

Q

14

13

12

11

SF00760

Q1

Q2

Q3

Q3

3