Philips 74F1763 Technical data

N74F1763N

INTEGRATED CIRCUITS

74F1763

Intelligent DRAM controller (IDC)

Product specification

1999 Jan 08

Supersedes data of 1989 Nov 17

IC15 Data Handbook

m n r

Philips Semiconductors	Product specification
Intelligent DRAM controller (IDC)	74F1763

FEATURES

•DRAM signal timing generator

•Automatic refresh circuitry

•Selectable row address hold and RAS precharge times

•Facilitates page mode accesses

•Controls 1 MBit DRAMs

•Intelligent burst-mode refresh after page-mode access cycles

PRODUCT DESCRIPTION

The Philips Semiconductors Intelligent Dynamic RAM Controller is a 1 MBit, single-port version of the 74F1764 Dual Port Dynamic RAM Controller. It contains automatic signal timing, address multiplexing and refresh control required for interfacing with dynamic RAMs. Additional features have been added to this device to take advantage of technological advances in Dynamic RAMs. A

Page-Mode access pin allows the user to assert RAS for the entire access cycle rather than the pre-defined four-clock-cycle pulse width used for normal random access cycles. In addition, the user has the

ability to select the RAS precharge time and Row-Address Hold time to fit the particular DRAMs being used. DTACK has been modified from previous family parts to become a negative true, tri-stated output. The options for latched or unlatched address are contained on a single device by the addition of an Address Latch Enable (ALE) input. Finally, a burst refresh monitor has been added to ensure complete refreshing after length page-mode access cycles. With a maximum clock frequency of 100 MHz, the F1763 is capable of controlling DRAM arrays with access times down to 40 nsec.

TYPE	fMAX	TYPICAL SUPPLY CURRENT
		(TOTAL)
74F1763	100 MHz	150 mA

ORDERING INFORMATION

	COMMERCIAL RANGE
PACKAGES	VCC = 5V 10%;	PKG DWG #
	TA = 0 C TO 70 C
48-pin Plastic DIP	N74F1763N	SOT240-1

INPUT AND OUTPUT LOADING FAN-OUT TABLENO TAG

PINS

DESCRIPTION

74F (U.L.) HIGH/LOW

LOAD VALUE HIGH/LOW

DRAM Request Input

1.0/1.0

20 Â A/0.6 mA

REQ

CP

Clock Input

1.0/1.0

20 Â A/0.6 mA

Page Mode Select Input

1.0/1.0

20 Â A/0.6 mA

PAGE

PRECHRG

Precharge Select Input

1.0/1.0

20 Â A/0.6 mA

RAS

HLDROW

Row Hold Select Input

1.0/1.0

20 Â A/0.6 mA

Data Transfer Ack. Output

50/80

35 mA/60 mA

DTACK

GNT

Access Grant Output

50/80

35 mA/60 mA

RCP

Refresh Clock Input

1.0/1.0

20 Â A/0.6 mA

RA0±9

Row Address Inputs

1.0/1.0

20 Â A/0.6 mA

CA0±9

Column Address Inputs

1.0/1.0

20 Â A/0.6 mA

Address Latch Enable Input

1.0/1.0

20 Â A/0.6 mA

ALE

Row Address Strobe Output

NA

35 mA/60 mA

RAS

Column Address Strobe Output

NA

35 mA/60 mA

CAS

MA0±9

DRAM Address Outputs

NA

35 mA/60 mA

NOTES:

One (1.0) FAST Unit Load is defined as 20 Â A in the HIGH state and 0.6 mA in the LOW state.

FAST Unit Loads do not correspond to DRAM Input Loads. See Functional Description for details.

1999 Jan 08

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853±1406 20619

Philips Semiconductors	Product specification
Intelligent DRAM controller (IDC)	74F1763

BLOCK DIAGRAM

RAS

CAS

PAGE
CP	RAS, CAS, MUX, DTACK
PRECHRG
HLDROW	TIMING
DTACK

REFRESH

REQ ARBITRATION

GNT

BURST REFRESH MONITOR

RCP REFRESH ADDRESS COUNTER

RA0±9	ROW ADDRESS LATCH
	MULTIPLEXER
	MA0±9
CA0±9	COLUMN ADDR. LATCH
ALE	SF01400

DIP PIN CONFIGURATION

PLCC PIN CONFIGURATION

		GNT				1		48		REQ
HLDROW						2		47		PAGE
										CP
PRECHRG						3		46
		RAS				4		45		RCP
		CAS				5		44		RA0
	DTACK					6		43		CA0
		MA0				7		42		RA1
										CA1
		MA1				8		41
		MA2				9		40		RA2
		MA3				10		39		CA2
								38
	GND					11				VCC
	GND
						12		37		VCC
	GND					13		36		VCC
	GND					14		35		RA3
		MA4				15		34		CA3
		MA5				16		33		RA4
		MA6				17		32		CA4
		MA7				18		31		RA5
		MA8				19		30		CA5
		MA9				20		29		RA6
						21		28	CA6
			ALE
		CA9				22		27		RA7
		RA9				23		26		CA7
		CA8				24		25		RA8

			DTACK				CAS			RAS		PRECHRG		HLDROW		GNT			REQ			PAGE		CP		RCP		RA0
			6		5				4			3		2		1		44			43			42		41		40
MA0	7																													39	CA0
MA1	8																													38	RA1
MA2	9																													37	CA1
MA3	10																													36	RA2
GND	11																													35	CA2
GND	12																													34	VCC
MA4
	13																													33	RA3
MA5
	14																													32	CA3
MA6
	15																													31	RA4
MA7	16																													30	CA4
MA8	17																													29	RA5
			18		19				20			21		22		23		24			25			26		27		28
			MA9				ALE			CA9		RA9		CA8		RA8			CA7			RA7		CA6		RA6		CA5

SF01401

SF01402

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Philips Semiconductors	Product specification
Intelligent DRAM controller (IDC)	74F1763

PIN DESCRIPTION

SYMBOL

PINS

TYPE

NAME AND FUNCTION

DIP

Active Low Memory Access Request input, must be asserted for the entire DRAM access cycle.

REQ

48

Input

REQ is sampled on the rising edge of the CP clock.

GNT

1

Output

Active High Grant output. When High indicates that a DRAM access (inactive during refresh)

cycle has begun. Asserted from the rising edge of the CP clock.

Active Low Page-Mode Access input. Forces the IDC to keep

asserted for as long as the

RAS

PAGE

47

Input

PAGE input is Low and REQ is asserted Low.

Row Address Hold input. If Low will configure the IDC to maintain the row addresses for a full

HLDROW

2

Input

CP clock cycle after

RAS

is asserted. If High will program the IDC to maintain row addresses for

a 1/2 CP clock cycle after

RAS

is asserted.

Precharge input. A Low will program the IDC to guarantee a minimum of 4 CP clock cycles

PRECHRG

3

Input

RAS

of precharge. A High will guarantee 3 clock cycles of precharge.

CP

46

Input

Clock input. Used by the Controller for all timing and arbitration functions.

RCP

45

Input

Refresh Clock input. Divided internally by 64 to produce an internal Refresh Request.

Active Low, 3-state Data Transfer Acknowledge output. Enabled by the

input and asserted

REQ

DTACK

6

Output

four clock cycles after the assertion of RAS, 3-stated when REQ goes High.

44, 42, 40,

RA0±9

35, 33, 31,

Inputs

Row Address inputs.

29, 27, 25,

23

43, 41, 39,

CA0±9

34, 32, 30,

Inputs

Column Address inputs. Propagated to the MA0±9 outputs 1 CP clock cycle after

RAS

is

28, 26, 24,

asserted, if HLDROW = 0 or 1/2 clock cycle later if HLDROW is 1.

22

Active Low Row Address Strobe. Asserted for four clock cycles during each refresh cycle

regardless of the

PAGE

input. Also asserted for four clock cycles during processor access if the

RAS

4

Output

PAGE input is High. If PAGE is Low, RAS is negated upon negation of PAGE or REQ, whichever

occurs first.

Active Low Column Address Strobe. Always asserted 1.5 CP clock cycles after the assertion of

CAS

5

Output

RAS. Negated upon negation of REQ. HLDROW input pin does not affect RAS to CAS timing.

MA0±9

7±10,

Output

DRAM multiplexed address outputs. Row and column addresses asserted on these pins during

15±20

an access cycle. Refresh counter addresses presented on these outputs during refresh cycles.

Active Low Address Latch Enable input. A Low on this pin will cause the address latches to be

ALE

21

Input

transparent. A High level will latch the RA0±9 and CA0±9 inputs.

VCC

36±38

+5V 10% Supply voltage.

GND

11±14

Ground

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Philips Semiconductors	Product specification
Intelligent DRAM controller (IDC)	74F1763

FUNCTIONAL DESCRIPTION

The 74F1763 1 Megabit Intelligent DRAM Controller (IDC) is a synchronous device with most signal timing being a function of the

CP input clock.

Arbitration

Once the DRAM's RAS precharge time has been satisfied, the REQ input is sampled on each rising edge of the CP clock and an internally generated refresh request is sampled on each falling edge of the same clock. When only one of these requests is sampled as active the appropriate memory cycle will begin immediately. For a

memory access cycle this will be indicated by GNT and RAS outputs both being asserted and for a refresh cycle by multiplexing refresh

address to the MA0±9 outputs and subsequent assertion of RAS after 1/2CP clock cycle. If both memory access and refresh requests are active at a given time the request sampled first will begin immediately and the other request (if still asserted) will be serviced

upon completion of the current cycle and it's associated RAS precharge time.

Memory access

The row (RA0±9) and column (CA0±9) address inputs are latched when ALE input is High. When ALE is Low the input addresses propagate directly to the outputs. When GNT and RAS are asserted, after a REQ has been sampled the RA0±9 address inputs will have already propagated to the MA0±9 outputs for the row address. One or one-half CP clock cycles later (depending on the state of the HLDROW input) the column address (CA0±9) inputs are propagated

to the MA0±9 outputs. CAS is always asserted one and one-half CP clock cycles after RAS is asserted. If the PAGE input is High, RAS will be negated approximately four CP clock cycles after its initial

assertion. At this time the DTACK output becomes valid indicating the completion of a memory access cycle. The IDC will maintain the state of all its outputs until the REQ input is negated ( see timing waveforms).

Row address hold times

If the HLDROW input of the IDC is High the row address outputs will

remain valid 1/2 CP clock cycle after RAS is asserted. If the HLDROW input is Low the row address outputs will remain valid one

CP clock cycle after RAS is asserted.

RAS precharge timing

In order to meet the RAS precharge requirement of dynamic RAMs, the controller will hold-off a subsequent RAS signal assertion due to a processor access request or a refresh cycle for four or three full CP clock cycles from the previous negation of RAS, depending on the state of the PRECHRG input. If the PRECHRG input is Low, RAS remains High for at least 4 CP clock cycles. If the PRECHRG input is High RAS remains High for at least 3 CP clock cycles.

Refresh timing

The refresh address counter wakes-up in an all 1's state and is an up counter. The refresh clock (RCP) is internally divided down by 64 to produce an internal refresh request. This refresh request is recognized either immediately or at the end of a running memory access cycle. Due to the possibility that page mode access cycles may be lengthy, the controller keeps track of how many refresh requests have been missed by logging them internally (up to 128) and servicing any pending refresh requests at the end of the

memory access cycle. The controller performs RAS-only refresh cycles until all pending refresh requests are depleted.

Page-mode access

Fast accesses to consecutive locations of DRAM can be realized by asserting the PAGE input as shown in the timing waveforms. In this mode, the controller does not automatically negate RAS after four CP clock cycles, but keeps it asserted throughout the access cycle. By using external gates, the CAS output can be gated on and off while changing the column address inputs to the controller, which will propagate to the MA0±MA9 address outputs and provide a new

column address. This is only useful if the ALE input is Low, enabling the user to charge addresses. This mode can be used with DRAMs that support page or nibble mode addressing.

Output driving characteristics

Considering the transmission line characteristic of the DRAM arrays, the outputs of the IDC have been designed to provide incident-edge switching (in Dual-Inline-Packaged memory arrays), needed in high performance systems. For more information on the driving characteristics, please refer to Philips Semiconductors application note AN218. The driving characteristics of the 74F1763 are the same as those of the 74F765 shown in the application note.

1999 Jan 08

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