Philips 74f175a DATASHEETS
INTEGRATED CIRCUITS
74F175A
Quad D flip-flop
Product specification
Supersedes data of 1996 Mar 12
IC15 Data Handbook
2000 Jun 30
Philips Semiconductors Product specification
74F175AQuad D flip-flop
FEA TURES
•Four edge-triggered D-type flip-flops
•Buffered common clock
•Buffered asynchronous Master Reset
•True and complementary outputs
•Industrial temperature range available (–40°C to +85°C)
•PNP light loading inputs
DESCRIPTION
The 74F175A is a quad, edge-triggered D-type flip-flop with
individual D inputs and both Q and Q
Clock (CP) and Master Reset (MR
flip-flops simultaneously.
The register is fully edge-triggered. The state of each D input, one
setup time before the Low-to-High clock transition is transferred to
the corresponding flip-flop’s Q output.
All Q outputs will be forced Low independently of clock or data
inputs by a Low voltage level on the MR
for applications where both true and complementary outputs are
required, and the CP and MR
ORDERING INFORMATION
DESCRIPTION
16-pin plastic DIP N74F175AN I74F175AN SOT38-4
16-pin plastic SO N74F175AD I74F175AD SOT109-1
outputs. The common buffered
) inputs load and reset (clear) all
input. The device is useful
are common to all storage elements.
COMMERCIAL RANGE
V
= 5V ±10%,
CC
= 0°C to +70°C
T
amb
PIN CONFIGURATION
TYPE TYPICAL f
74F175A 160MHz 22mA
ORDER CODE
INDUSTRIAL RANGE
V
T
amb
1
MR
Q0
2
0
Q
3
D0
4
D1
5
Q
1
6
Q1
GND
max
= 5V ±10%,
CC
= –40°C to +85°C
16
V
CC
Q3
15
3
Q
14
D3
13
D2
12
Q
2
11
Q2
107
98
CP
SF00718
TYPICAL SUPPL Y
CURRENT (TOTAL)
PKG. DWG. #
INPUT AND OUTPUT LOADING AND FAN OUT TABLE
PINS DESCRIPTION
74F (U.L.)
HIGH/LOW
D0 – D3 Data inputs 74F175A 1.0/0.033 20µA/20µA
MR Master reset input (active–Low) 74F175A 1.0/0.033 20µA/20µA
CP Clock input (active rising edge) 74F175A 1.0/0.033 20µA/20µA
Q0–Q3 True outputs 50/33 1.0mA/20mA
Q0–Q3 Complementary outputs 50/33 1.0mA/20mA
NOTE:
One (1.0) FAST unit load is defined as: 20µA in the High state and 0.6mA in the Low state.
2000 Jun 30 853–0047 24024
2
LOAD VALUE
HIGH/LOW
Philips Semiconductors Product specification
T
O erating free air tem erature range
74F175AQuad D flip-flop
LOGIC SYMBOL
9
1
VCC = Pin 16
GND = Pin 8
LOGIC DIAGRAM
= Pin 16
V
CC
GND = Pin 8
4 5 12 13
D0 D1 D2 D3
CP
MR
Q0 Q0 Q1 Q1 Q2 Q2 Q3 Q3
2 3 7 6 10 11 15 14
9
CP
1
MR
SF00719
D0
4
DQ
CP
IEC/IEEE SYMBOL
1
9
4
5
12
13
D1
5
DQ
RD
32 6 1110 14157
Q
0Q0 Q1Q1 Q2Q2 Q3Q3
CP
RD
D2
12
DQ
CP
RD
D3
13
DQ
CP
RD
R
C1
2
1D
Q
SF00721
3
7
6
10
11
15
14
SF00720
FUNCTION TABLE
INPUTS OUTPUTS
MR CP Dn Q
n
Q
n
OPERATING
MODE
L X X L H Reset (clear)
H ↑ h H L Load “1”
H ↑ I L H Load “0”
H = High voltage level
h = High state must be present one setup time before the
Low-to-High clock transition
L = Low voltage level
l = Low state must be present one setup time before the
Low-to-High clock transition
X = Don’t care
↑ = Low-to-High clock transition
ABSOLUTE MAXIMUM RATINGS
(Operation beyond the limit set forth in this table may impair the useful life of the device.
Unless otherwise noted these limits are over the operating free air temperature range.)
SYMBOL PARAMETER RATING UNIT
V
I
V
V
I
OUT
T
Supply voltage –0.5 to +7.0 V
CC
Input voltage –0.5 to +7.0 V
IN
Input current –30 to +5 mA
IN
Voltage applied to output in High output state –0.5 to V
OUT
Current applied to output in Low output state
40 mA
Commercial range 0 to +70
amb
stg
p
Storage temperature range –65 to +150
p
Industrial range –40 to +85
CC
V
°C
°C
°C
2000 Jun 30
3
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