Philips 74f174 DATASHEETS
INTEGRATED CIRCUITS
74F174
Hex D flip-flops
Product specification
IC15 Data Handbook
1988 Oct 07
Philips Semiconductors Product specification
74F174Hex D flip-flop
FEA TURES
PIN CONFIGURATION
•Six edge-triggered D-type flip-flops
•Buffered common Clock
MR
•Buffered, asynchronous Master Reset
DESCRIPTION
The 74F174 has six edge-triggered D-type flip-flops with individual D
inputs and Q outputs. The common buffered Clock (CP) and Master
Reset (MR
The register is fully edge-triggered. The state of each D input, one
setup time before the Low-to-High clock transition is transferred to
the corresponding flip-flop’s Q output.
All Q outputs will be forced Low independent of Clock or Data inputs
by a Low voltage level on the MR
applications where true outputs only are required, and the Clock and
Master Reset are common to all storage elements.
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
NOTE: One (1.0) FAST unit load is defined as: 20µA in the High state and 0.6mA in the Low state.
) inputs load and reset (clear) all flip-flops simultaneously.
input. The device is useful for
ORDERING INFORMA TION
TYPICAL
TYPE
TYPICAL f
MAX
SUPPLY CURRENT
(TOTAL)
74F174 100MHz 35mA
PINS DESCRIPTION 74F (U.L.) HIGH/LOW LOAD VALUE HIGH/LOW
D0–D5 Data inputs 1.0/1.0 20µA/0.6mA
CP Clock Pulse input (active rising edge) 1.0/1.0 20µA/0.6mA
MR Master Reset input (active-Low) 1.0/1.0 20µA/0.6mA
Q0–Q5 Outputs 50/33 1.0mA/20mA
DESCRIPTION
16-pin plastic DIP N74F174N SOT38-4
16-pin plastic SO N74F174D SOT109-1
1
2
Q0
3
D0
4
D1
5
Q1
6
D2
Q2
COMMERCIAL RANGE
VCC = 5V ±10%,
T
= 0°C to +70°C
amb
16
15
14
13
12
11
107
98GND CP
SF00188
V
Q5
D5
D4
Q4
D3
Q3
CC
PKG DWG #
LOGIC SYMBOL
346
D0 D1 D2 D3 D4 D5
V
= Pin 16
CC
GND = Pin 8
9
1
CP
MR
Q1
5Q02
October 7, 1988 853–0060 94766
11 13 14
Q2 Q3 Q4 Q5
7101215
SF00189
IEC/IEEE SYMBOL
2
9
1
3
4
6
11
13
14
C1
R
1D
2
5
7
10
12
15
SF00190
Philips Semiconductors Product specification
OPERATING MODE
SYMBOL
PARAMETER
UNIT
74F174Hex D flip-flop
LOGIC DIAGRAM
D0
3
D1
4
D2
6
D3
11
D4
13
D5
14
= Pin 16
V
CC
GND = Pin 8
CP
MR
Q
D
CP
R
D
9
1
2
Q0
Q
D
CP
R
D
5
Q1
Q
D
CP
R
D
7
Q2
FUNCTION TABLE
INPUTS OUTPUTS
MR CP D Qn
L X X L Reset (clear)
H ↑ hH Load “1”
H ↑ l L Load “0”
H = High voltage level
L = Low voltage level
X = Don’t care
↑ = Low-to-High Clock transition
h = High voltage level one set-up time prior to the Low-to-High Clock transition.
l = Low voltage level one set-up time prior to the Low-to-High Clock transition.
ABSOLUTE MAXIMUM RATINGS
(Operation beyond the limits set forth in this table may impair the useful life of the device.
Unless otherwise noted these limits are over the operating free-air temperature range.)
SYMBOL
V
CC
V
IN
I
IN
V
OUT
I
OUT
T
amb
T
stg
Supply voltage –0.5 to +7.0 V
Input voltage –0.5 to +7.0 V
Input current –30 to +5 mA
Voltage applied to output in High output state –0.5 to V
Current applied to output in Low output state 40 mA
Operating free-air temperature range 0 to +70 °C
Storage temperature range –65 to +150 °C
PARAMETER RATING UNIT
Q
D
CP
R
D
10
Q3
Q
D
CP
R
D
12
Q4
D
CC
CP
R
Q
D
15
Q5
SF00192
V
RECOMMENDED OPERATING CONDITIONS
V
CC
V
IH
V
IL
I
IK
I
OH
I
OL
T
amb
October 7, 1988
Supply voltage 4.5 5.0 5.5 V
High-level input voltage 2.0 V
Low-level input voltage 0.8 V
Input clamp current –18 mA
High-level output current –1 mA
Low-level output current 20 mA
Operating free-air temperature range 0 +70 °C
LIMITS
MIN NOM MAX
3
Loading...