Philips 74f164 DATASHEETS
INTEGRATED CIRCUITS
74F164
8-bit serial-in parallel-out shift register
Product specification 1995 Sep 22
IC15 Data Handbook
Philips Semiconductors Product specification
DRAWING
74F1648-bit serial-in parallel-out shift register
FEA TURES
PIN CONFIGURATION
•Gated serial data inputs
1
•Typical shift frequency of 100MHz
•Asynchronous Master Reset
•Buffered clock and data inputs
•Fully synchronous data transfer
•Industrial temperature range available (–40°C to +85°C)
DESCRIPTION
Dsa
Dsb
GND
Q0
Q1
Q2
Q3
2
3
4
5
6
The 74F164 is an 8-bit edge-triggered shift register with serial data
entry and an output from each of the eight stages. Data is entered
through one of two inputs (Dsa, Dsb); either input can be used as an
active High enable for data entry through the other input. Both inputs
must be connected together or an unused input must be tied High.
Data shifts one place to the right on each Low-to-High transition of
the clock (CP) input, and enters into Q0 the logical AND of the two
data inputs (Dsa, Dsb) that existed one setup time before the rising
edge. A Low level on the Master Reset (MR
) input overrides all
TYPE TYPICAL f
74F164 100MHz 33mA
max
other inputs and clears the register asynchronously, forcing all
outputs Low.
ORDERING INFORMATION
ORDER CODE
DESCRIPTION
14-pin plastic DIP 74F164N I74F164N SOT27-1
14-pin plastic SO 74F164D I74F164D SOT108-1
COMMERCIAL RANGE
VCC = 5V ±10%, T
= 0°C to +70°C
amb
VCC = 5V ±10%, T
INDUSTRIAL RANGE
= –40°C to +85°C
amb
14
V
CC
13
Q7
12
Q6
11
Q5
10
Q4
9
MR
CP
87
SF00717
TYPICAL SUPPL Y
CURRENT (TOTAL)
NUMBER
INPUT AND OUTPUT LOADING AND FAN OUT TABLE
PINS DESCRIPTION
Dsa, Dsb Data inputs 1.0/1.0 20µA/0.6mA
CP Clock pulse input (active rising edge) 1.0/1.0 20µA/0.6mA
MR Master reset input (active-Low) 1.0/1.0 20µA/0.6mA
Q0 – Q7 Data outputs 50/33 1.0mA/20mA
One (1.0) FAST unit load is defined as: 20µA in the High state and 0.6mA in the Low state.
LOGIC SYMBOL
8
9
V
= Pin 14
CC
GND = Pin 7
12
CP
MR
Dsa Dsb
Q0
Q1 Q3 Q4
3 4 5 6 10 11 12 13
Q0 Q1 Q3 Q4
SF00713
IEC/IEEE SYMBOL
74F (U.L.)
HIGH/LOW
LOAD VALUE
HIGH/LOW
R
SRG8
C1/→
&
1D
3
4
5
6
10
11
12
13
SF00714
8
9
1
2
1995 Sep 22 853-0348 15794
2
Philips Semiconductors Product specification
T
O erating free-air tem erature range
°C
SYMBOL
PARAMETER
UNIT
T
O erating free-air tem erature range
°C
74F1648-bit serial-in parallel-out shift register
LOGIC DIAGRAM
1
Dsa
2
Dsb
8
CP
9
V
= Pin 14
CC
GND = Pin 7
MR
FUNCTION TABLE
INPUTS OUTPUTS OPERATING MODE
MR CP Dsa Dsb Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
L X X X L L L L L L L L Reset (Clear)
H ↑ l l L q0 q1 q2 q3 q4 q5 q6
H ↑ l h L q0 q1 q2 q3 q4 q5 q6 Shift
H ↑ h l L q0 q1 q2 q3 q4 q5 q6
H ↑ h h H q0 q1 q2 q3 q4 q5 q6
H = High voltage level
h = High voltage level one setup time prior to the Low-to-High clock transition.
L = Low voltage level
l = Low voltage level one setup time prior to the Low-to-High clock transition.
qn = Lower case letter indicate the state of the referenced output one setup time prior to the Low-to-High clock transition.
X = Don’t care
↑ = Low-to-High clock transition
DQ
RD
Q0
3
DQ
RD
Q1
DQ
4
RD
Q2
DQ
5
RD
Q3
6
DQ
RD
Q4
10
DQ
RD
Q5
11
DQ
RD
Q6
12
DQ
CPCPCPCPCPCPCPCP
RD
Q7
13
SF00715
ABSOLUTE MAXIMUM RATINGS
(Operation beyond the limit set forth in this table may impair the useful life of the device.
Unless otherwise noted these limits are over the operating free air temperature range.)
SYMBOL PARAMETER RATING UNIT
V
V
I
IN
V
I
OUT
T
CC
IN
OUT
amb
stg
Supply voltage –0.5 to +7.0 V
Input voltage –0.5 to +7.0 V
Input current –30 to +5 mA
Voltage applied to output in High output state –0.5 to V
CC
Current applied to output in Low output state 40 mA
p
p
Commercial Range 0 to +70
Industrial Range –40 to +85
Storage temperature range –65 to +150 °C
RECOMMENDED OPERATING CONDITIONS
LIMIT
MIN NOM MAX
V
V
V
I
I
OH
I
OL
amb
Supply voltage 4.5 5.0 5.5 V
CC
High-level iput voltage 2.0 V
IH
Low-level input voltage 0.8 V
IL
Input clamp current –18 mA
Ik
High-level output current –1 mA
Low-level output current 20 mA
p
p
Commercial Range 0 +70
Industrial Range –40 +85
V
°
°
1995 Sep 22
3
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