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74F163A |
INTEGRATED CIRCUITS |
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74F160A*, 74F161A, 74F162A*, 74F163A
4-bit binary counter
* Discontinued part. Please see the Discontinued Product List in Section 1, page 21.
Product specification |
1996 Jan 29 |
IC15 Data Handbook
m n r
Philips Semiconductors |
Product specification |
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4-bit binary counters |
74F161A, 74F163A |
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FEATURES
•Synchronous counting and loading
•Two count enable inputs for n-bit cascading
•Positive edge-triggered clock
•Asynchronous Master Reset (74F161A)
•Synchronous Reset (74F163A)
•High speed synchronous expansion
•Typical count rate of 130MHz
•Industrial range (±40°C to +85°C) available
DESCRIPTION
4-bit binary counters feature an internal carry look-ahead and can be used for high-speed counting. Synchronous operation is provided by having all flip-flops clocked simultaneously on the positive-going edge of the clock. The clock input is buffered.
The outputs of the counters may be preset to High or Low level. A
Low level at the Parallel Enable (PE) input disables the counting action and causes the data at the D0±D3 inputs to be loaded into the counter on the positive-going edge of the clock (provided that the setup and hold requirements for PE are met). Preset takes place regardless of the levels at Count Enable (CEP, CET) inputs.
A Low level at the Master Reset (MR) input sets all the four outputs of the flip-flops (Q0 ± Q3) in 74F161A to Low levels, regardless of the levels at CP, PE, CET and CEP inputs (thus providing an asynchronous clear function). For the 74F163A, the clear function is synchronous. A Low level at the Synchronous Reset (SR) input sets all four outputs of the flip-flops (Q0 ± Q3) to Low levels after the next positive-going transition on the clock (CP) input (provided that the setup and hold time requirements for SR are met). This action occurs regardless of the levels at PE, CET, and CEP inputs. The synchronous reset feature enables the designer to modify the maximum count with only one external NAND gate (see Figure 1). The carry look-ahead simplifies serial cascading of the counters. Both Count Enable (CEP and CET) inputs must be High to count. The CET input is fed forward to enable the TC output. The TC output thus enabled will produce a High output pulse of a duration approximately equal to the High level output of Q0. This pulse can be used to enable the next cascaded stage (see Figure 2). The TC output is subjected to decoding spikes due to internal race conditions. Therefore, it is not recommended for use as clock or asynchronous reset for flip-flops, registers, or counters.
TYPE |
TYPICAL |
TYPICAL SUPPLY CURRENT |
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fMAX |
(TOTAL) |
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74F161A |
130MHz |
46mA |
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74F163A |
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ORDERING INFORMATION
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ORDER CODE |
DRAWING |
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DESCRIPTION |
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COMMERCIAL RANGE |
INDUSTRIAL RANGE |
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NUMBER |
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VCC = 5V ±10%, Tamb = 0°C to +70°C |
VCC = 5V ±10%, Tamb = ±40°C to +85°C |
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16-pin plastic DIP |
N74F161AN, N74F163AN |
I74F161AN, I74F163AN |
SOT38-4 |
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16-pin plastic SO |
N74F161AD, N74F163AD |
I74F161AD, I74F163AD |
SOT109-1 |
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INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
PINS |
DESCRIPTION |
74F (U.L.) HIGH/LOW |
LOAD VALUE HIGH/LOW |
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D0 ± D3 |
Data inputs |
1.0/1.0 |
20μA/0.6mA |
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CEP |
Count Enable Parallel input |
1.0/1.0 |
20μA/0.6mA |
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CET |
Count Enable Trickle input |
1.0/2.0 |
20μA/1.2mA |
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CP |
Clock input (active rising edge) |
1.0/1.0 |
20μA/0.6mA |
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Parallel Enable input (active Low) |
1.0/2.0 |
20μA/1.2mA |
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PE |
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Asynchronous Master Reset input |
1.0/1.0 |
20μA/0.6mA |
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MR |
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(active Low) for 74F161A |
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Synchronous Reset input |
1.0/1.0 |
20μA/0.6mA |
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SR |
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(active Low) for 74F163A |
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TC |
Terminal count output |
50/33 |
1.0mA/20mA |
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Q0 ± Q3 |
Flip-flop outputs |
50/33 |
1.0mA/20mA |
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NOTE:
One (1.0) FAST unit load is defined as: 20μA in the High state and 0.6mA in the Low state.
1996 Jan 29 |
2 |
853±0347 16300 |
Philips Semiconductors |
Product specification |
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4-bit binary counters |
74F161A, 74F163A |
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74F161A PIN CONFIGURATION
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MR |
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1 |
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16 |
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VCC |
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CP |
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TC |
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2 |
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D0 |
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Q0 |
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3 |
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D1 |
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Q1 |
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D2 |
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Q2 |
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D3 |
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Q3 |
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CEP |
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CET |
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10 |
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GND |
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8 |
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PE |
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SF00656 |
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74F161A LOGIC SYMBOL |
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3 |
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9 |
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PE |
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D0 |
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D2 |
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D3 |
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CEP |
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CET |
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TC |
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CP |
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1 |
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MR |
Q0 |
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Q2 |
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VCC = Pin 16 |
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14 |
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11 |
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GND = Pin 8 |
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SF00658 |
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74F161A LOGIC SYMBOL (IEEE/IEC) |
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1 |
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R |
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CTR DIV 16 |
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M1 |
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G3 |
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G4 |
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C2 /1,3,4+ |
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1,2 D |
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74F163A PIN CONFIGURATION
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SR |
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CP |
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TC |
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15 |
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D0 |
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Q0 |
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D1 |
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Q1 |
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D2 |
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Q2 |
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D3 |
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Q3 |
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CEP |
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CET |
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7 |
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10 |
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GND |
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8 |
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9 |
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PE |
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SF00657 |
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74F163A LOGIC SYMBOL |
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9 |
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PE |
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D0 |
D1 |
D2 |
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7 |
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CEP |
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10 |
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CET |
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TC |
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2 |
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CP |
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1 |
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SR |
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Q0 |
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Q3 |
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VCC = Pin 16 |
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14 |
13 |
12 |
11 |
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GND = Pin 8 |
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SF00659 |
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74F163A LOGIC SYMBOL (IEEE/IEC) |
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1 |
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2R |
CTR DIV 16 |
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9 |
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M1 |
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7 |
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G3 |
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10 |
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G4 |
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2 |
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C2 /1,3,4+ |
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3 |
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14 |
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1,2 D |
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4 |
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13 |
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5 |
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6 |
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11 |
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15 |
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4 CT=15 |
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SF00660 |
SF00661 |
1996 Jan 29 |
3 |
Philips Semiconductors |
Product specification |
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4-bit binary counters |
74F161A, 74F163A |
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STATE DIAGRAM |
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APPLICATIONS |
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+VCC |
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0 |
1 |
2 |
3 |
4 |
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PE |
D0 |
D1 |
D2 |
D3 |
15 |
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5 |
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CEP |
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CET |
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74F163A |
TC |
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14 |
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6 |
CLOCK |
CP |
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SR |
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Q0 |
Q1 |
Q2 |
Q3 |
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13 |
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7 |
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12 |
11 |
10 |
9 |
8 |
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SF00665 |
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Figure 1. Maximum count modifying scheme
Terminal count = 6
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SF00664 |
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H H = Enable count |
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or |
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L L = Disable count |
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PE D0 D1 D2 D3 |
PE D0 D1 D2 D3 |
PE D0 D1 D2 D3 |
PE D0 D1 D2 D3 |
PE D0 D1 D2 D3 |
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CEP |
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CEP |
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CEP |
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CEP |
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CEP |
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CET |
74F163A |
TC |
CET |
74F163A |
TC |
CET |
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74F163A |
TC |
CET |
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74F163A |
TC |
CET |
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74F163A |
TC |
CP |
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CP |
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CP |
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CP |
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CP |
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SR Q0 Q1 Q2 Q3 |
SR |
Q0 Q1 Q2 |
Q3 |
SR |
Q0 |
Q1 Q2 |
Q3 |
SR |
Q0 |
Q1 Q2 |
Q3 |
SR |
Q0 |
Q1 Q2 |
Q3 |
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CP |
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SF00666 |
Figure 2. Synchronous multistage counting scheme
74F161A MODE SELECT ± FUNCTION TABLE
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INPUTS |
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OUTPUTS |
OPERATING MODE |
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CP |
CEP |
CET |
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Dn |
Qn |
TC |
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MR |
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PE |
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L |
X |
X |
X |
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X |
X |
L |
L |
Reset (clear) |
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H |
↑ |
X |
X |
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l |
l |
L |
L |
Parallel load |
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H |
↑ |
X |
X |
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l |
h |
H |
(1) |
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H |
↑ |
h |
h |
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h |
X |
count |
(1) |
Count |
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H |
X |
l |
X |
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h |
X |
qn |
(1) |
Hold (do nothing) |
||
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H |
X |
X |
l |
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h |
X |
qn |
L |
|||
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|
1996 Jan 29 |
4 |
Philips Semiconductors |
Product specification |
|
|
|
|
4-bit binary counters |
74F161A, 74F163A |
|
|
|
|
74F163A MODE SELECT ± FUNCTION TABLE
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INPUTS |
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OUTPUTS |
OPERATING MODE |
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SR |
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CP |
CEP |
CET |
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PE |
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Dn |
Qn |
TC |
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l |
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↑ |
X |
X |
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X |
X |
L |
L |
Reset (clear) |
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h |
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↑ |
X |
X |
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l |
l |
L |
L |
Parallel load |
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h |
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↑ |
X |
X |
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l |
h |
H |
(2) |
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h |
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↑ |
h |
h |
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h |
X |
count |
(2) |
Count |
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h |
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X |
l |
X |
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h |
X |
qn |
(2) |
Hold (do nothing) |
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h |
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X |
X |
l |
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h |
X |
qn |
L |
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||||||||||
H |
= |
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High voltage level |
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h |
= |
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High voltage level one setup prior to the Low-to-High clock transition |
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||||||||
L |
= |
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Low voltage level |
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l |
= |
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Low voltage level one setup prior to the Low-to-High clock transition |
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||||||||
qn |
= |
|
Lower case letters indicate the state of the referenced output prior to the Low-to-High clock transition |
||||||||||
X |
= |
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Don't care |
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↑= Low-to-High clock transition
(1)= The TC output is High when CET is High and the counter is at Terminal Count (HHHH for 74F161A)
(2)= The TC output is High when CET is High and the counter is at Terminal Count (HHHH for 74F163A)
74F161A LOGIC DIAGRAM
CP |
2 |
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MR |
1 |
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PE |
9 |
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10 |
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CET |
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7 |
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CEP |
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D0 |
3 |
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D |
R Q |
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14 |
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CP |
Q |
Q0 |
D1 |
4 |
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D |
R Q |
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CP |
Q |
13 |
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Q1 |
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D2 |
5 |
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D |
R Q |
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CP |
Q |
12 |
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Q2 |
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D3 |
6 |
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D |
R Q |
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CP |
Q |
11 |
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Q3 |
||
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15 |
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TC |
VCC = Pin 16 |
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GND = Pin 8 |
|
|
SF00662 |
|
|
|
|
1996 Jan 29 |
5 |
|
|