Philips 74f1604 DATASHEETS
INTEGRATED CIRCUITS
74F1604
Latch
Product specification
IC15 Data Handbook
1990 Oct 04
Philips Semiconductors Product specification
74F1604Latch
FEA TURES
• High impedance NPN base inputs for reduced loading
(20µA in high and low state)
• Stores 16–bit wide data inputs, multiplexed 8–bit outputs
• Propagation delay 7.0ns typical
• Power supply current 70mA typical
DESCRIPTION
The 74F1604 is a dual octal transparent latch. Organized as 8–bit A
and B latches, the latch outputs are connected by pairs to eight
2–input multiplexers. A select (SELECT A/B
whether the A or B latch contents are multiplexed to the eight
outputs. Data from the B inputs are selected when SELECT A/B
low; data from the A inputs are selected when SELECT A/B
Data enters the latch on the falling edge of the latch enable (LE
input. The latch remains transparent to the data inputs while LE
low, and stores the data that is present one setup time before the
low–to–high latch enable transition.
TYPICAL
TYPE
PROPAGATION DELAY
74F1604 7.0ns 70mA
ORDERING INFORMATION
ORDER CODE
DESCRIPTION COMMERCIAL RANGE
= 5V ±10%,
V
CC
T
= 0°C to +70°C
amb
28–pin plastic DIP N74F1604N SOT117-2
28–pin plastic SOL N74F1604D SOT136-1
INPUT AND OUTPUT LOADING AND FAN OUT TABLE
PINS DESCRIPTION
A0 – A7 Data inputs 1.0/0.033 20µA/20µA
B0 – B7 Data inputs 1.0/0.033 20µA/20µA
SELECT
A/B
Q0 – Q7 Data outputs 50/33 1.0mA/20mA
Note to input and output loading and fan out table
One (1.0) FAST unit load is defined as: 20µA in the high state and
0.6mA in the low state.
Select input 1.0/0.033
Latch enable input
LE
(active low)
) input determines
TYPICAL SUPPL Y
CURRENT (TOTAL)
74F (U.L.)
HIGH/LOW
1.0/0.033
is
is high.
)
is
PKG DWG #
LOAD VALUE
HIGH/LOW
20µA/20µA
20µA/20µA
PIN CONFIGURATION
1
LE
SELECT A/B
2
A0
3
B0
4
A1
5
B1
6
A2
7
B2
8
A3
9
B3
10 19
Q3
11
Q2
12
Q1
13
GND
14 15
LOGIC SYMBOL
34 56789102726252423222120
A0 B0 A1 B1 A2 B2 A3 B3 A4 B4 A5 B5 A6B6A7 B7
1
LE
2
SELCT A/B
Q0Q1Q2Q3Q4 Q5Q6Q7
VCC = Pin 28
GND = Pin 14
15 13 12 1 1 16 17 18 19
IEC/IEEE SYMBOL
2
1
3
4
5
6
7
8
9
10
27
26
25
24
23
22
21
20
G2
C1
1D 2
1D 2
28
V
27
A4
26
B4
25
A5
24
B5
23
A6
22
B6
A7
21
B7
20
Q7
Q6
18
Q5
17
Q4
16
Q
SF00553
1
CC
SF00554
15
13
12
11
16
17
18
19
SF00555
October 4, 1990 853 0088 00619
2
Philips Semiconductors Product specification
Enable and read register
Latch and read register
74F1604Latch
LOGIC DIAGRAM
SELECT A/B
2
1
LE
V
= Pin 28
CC
GND = Pin 14
3
A0
4
B0
A1
B1
A2
B2
A3
10
B3
27
A4
26
B4
25
A5
24
B5
23
A6
22
B6
21
A7
20
B7
D
Q
E
5
6
D
Q
E
7
8
D
Q
E
9
D
Q
E
D
Q
E
D
Q
E
D
Q
E
D
Q
E
D
Q
E
D
Q
E
D
Q
E
D
Q
E
D
Q
E
D
Q
E
D
Q
E
D
Q
E
15
13
12
11
16
17
18
19
SF00556
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
FUNCTION TABLE
OPERATING MODE
Notes to function table
H = High–voltage level
h = High–voltage level one setup time before the low–to–high latch enable transition
L = Low–voltage level
l = Low–voltage level one setup time before the low–to–high latch enable transition
NC= No change ( If SELECT A/B
X = Don’t care
↑ = Low–to–high latch enable transition
October 4, 1990
INPUTS OUTPUTS OUTPUTS
A0 – A7 B0 –B7 SELECT A/B LE Q0 – Q7
A data B data L L B data
A data B data H L A data
X X X H NC Hold
A data B data l ↑ B data
A data B data h ↑ A data
is toggled and the A latched data is different from B latched data then the output will change accordingly .)
3
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