Philips 74f153 DATASHEETS
INTEGRATED CIRCUITS
74F153
Dual 4-line to 1-line multiplexer
Product specification 1996 Jan 05
IC15 Data Handbook
Philips Semiconductors Product specification
74F153Dual 4-line to 1-line multiplexer
FEA TURES
PIN CONFIGURATION
•Non-inverting outputs
•Separate enable for each section
•Common select inputs
•See 74F253 for 3-State version
DESCRIPTION
The 74F153 is a dual 4-input multiplexer that can select 2 bits of
data from up to four sources selected by common Select inputs (S0,
S1). The two 4-input multiplexer circuits have individual active-Low
Enables (E
independently. Outputs (Ya, Yb) are forced Low when the
corresponding Enables (E
The 74F153 is the logic implementation of a 2-pole, 4-position
switch where the switch is determined by the logic levels supplied to
the common select inputs.
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
NOTE: One (1.0) FAST unit load is defined as: 20µA in the High state and 0.6mA in the Low state.
a, Eb) which can be used to strobe the outputs
a, Eb) are High.
ORDERING INFORMA TION
DESCRIPTION
TYPICAL
TYPE
PROPAGATION
DELA Y
74F153 7.0ns 12mA
PINS DESCRIPTION 74F (U.L.) HIGH/LOW LOAD VALUE HIGH/LOW
I0a – I3a Port A data inputs 1.0/1.0 20µA/0.6mA
I0b – I3b Port B data inputs 1.0/1.0 20µA/0.6mA
S0, S1 Common Select inputs 1.0/1.0 20µA/0.6mA
Ea Port A Enable input (active Low) 1.0/1.0 20µA/0.6mA
Eb Port B Enable input (active Low) 1.0/1.0 20µA/0.6mA
Ya, Yb Port A, B data outputs 50/33 1.0µA/20mA
TYPICAL
SUPPLY CURRENT
(TOTAL)
16-pin plastic DIP N74F153N SOT38-4
16-pin plastic SO N74F153D SOT109-1
I3a
I2a
I1a
I0a
1
a
E
2
S1
3
4
5
6
Ya
SF00146
COMMERCIAL RANGE
VCC = 5V ±10%,
= 0°C to +70°C
T
amb
16
15
14
13
12
11
107
98GND Yb
V
E
S0
I3b
I2b
I1b
I0b
CC
b
PKG.
DWG. #
LOGIC SYMBOL
I1a I2a
43
I3aI0a
Ya
7
10 11
Yb
9
I1b I2b
12 13
I3bI0b
SF00147
65
14
2
1
15
V
= Pin 16
CC
GND = Pin 8
S0
S1
Ea
Eb
1996 Jan 05 853–0100 16187
IEC/IEEE SYMBOL
2
14
2
1
6
5
4
3
15
10
11
12
13
EN
0
0
G
3
1
MUX
0
1
2
3
7
9
SF00148
Philips Semiconductors Product specification
74F153Dual 4-line to 1-line multiplexer
LOGIC DIAGRAM
a EbI0a I1a I2a I3a S1 S2 I0b I0b I2b I3b
E
1 65432141011121315
V
= Pin 16
CC
GND = Pin 8
7
Ya Yb
9
SF00149A
FUNCTION TABLE
INPUTS OUTPUT
S0 S1 En I0n I1n I2n I3n Yn
X X H X X X X L
L L L L X X X L
L L L H X X X H
H L L X L X X L
H L L X H X X H
L H L X X L X L
L H L X X H X H
H H L X X X L L
H H L X X X H H
H = High voltage level
L = Low voltage level
X = Don’t care
1996 Jan 05
3
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