Philips 74avcm162836 DATASHEETS
INTEGRATED CIRCUITS
74AVCM162836
20-bit registered driver with inverted
register enable with 15 Ω termination
resistors (3-State)
Product specification 1999 Sep 30
Philips Semiconductors Preliminary specification
1
CPDPower dissi ation ca acitance er buffer
V
GND to V
1
F
20-bit registered driver with inverted register enable
with 15Ω termination resistors (3-State)
FEA TURES
•Wide supply voltage range of 1.2 V to 3.6 V
•Complies with JEDEC standard no. 8-1A/5/7.
•CMOS low power consumption
•Input/output tolerant up to 3.6 V
•Low inductance multiple V
and ground bounce
DESCRIPTION
The 74AVCM162836 is a 20-bit universal bus driver. Data flow is
controlled by output enable (OE
(CP).
This product is designed to have an extremely fast propagation
delay and a minimum amount of power consumption.
To ensure the high-impedance state during power up or power
down, OE
Insertion).
should be tied to VCC through a pullup resistor (Live
and GND pins for minimum noise
CC
), latch enable (LE) and clock inputs
PIN CONFIGURATION
1
2
Y
0
3
Y
1
4
GND
5
Y
2
6
Y
3
7
V
CC
8
Y
4
9
Y
5
Y
10
6
GND
11
Y
12
7
Y
13
8
14
Y
9
15
Y
10
16
Y
11
17
Y
12
18
GND
19
Y
13
20
Y
14
21
Y
15
22
V
CC
23
Y
16
24
Y
17
25
GND
26
Y
18
27
Y
19
28 29
NC
74A VCM162836
CP
56OE
A
55
0
54
A
1
53
GND
52
A
2
51
A
3
50
V
CC
49
A
4
48
A
5
A
47
6
GND
46
A
45
7
A
44
8
43
A
9
42
A
10
41
A
11
40
A
12
39
GND
38
A
13
37
A
14
36
A
15
35
V
CC
34
A
16
33
A
17
32
GND
31
A
18
30
A
19
LE
QUICK REFERENCE DA TA
GND = 0 V; T
SYMBOL
t
PHL/tPLH
t
PHL/tPLH
C
I
NOTES:
1. C
is used to determine the dynamic power dissipation (PD in µW):
PD
= CPD × V
P
D
= output frequency in MHz; VCC = supply voltage in V; S (CL × V
f
o
= 25°C; tr = tf ≤ 2.0 ns; CL = 30 pF.
amb
Propagation delay
An to Yn
Propagation delay
LE to Yn;
CP to Yn
Input capacitance 5.0 pF
2
× fi + S (CL × V
CC
ORDERING INFORMATION
56-Pin Plastic Thin Shrink Small Outline (TSSOP) Type II –40°C to +85°C 74AVCM162836 DGG SOT364-1
1999 Sep 30 853–2175 22452
SH00159
PARAMETER CONDITIONS TYPICAL UNIT
p
CC
p
2
PACKAGES
VCC = 1.8 V
VCC = 2.5 V
VCC = 3.3 V
VCC = 1.8 V
VCC = 2.5 V
VCC = 3.3 V
p
× fo) where: fi = input frequency in MHz; CL = output load capacitance in pF;
=
I
CC
CC
2
× fo) = sum of outputs.
TEMPERATURE
RANGE
Outputs enabled 25
Output disabled 6
ORDER CODE
2.6
2.0
1.7
3.0
2.4
2.0
2
ns
ns
p
DRAWING
NUMBER
Philips Semiconductors Preliminary specification
OUTPUTS
20-bit registered driver with inverted register enable
with 15Ω termination resistors (3-State)
PIN DESCRIPTION
PIN NUMBER SYMBOL NAME AND FUNCTION
28 NC No connection
2, 3, 5, 6, 8, 9, 10, 12,
13, 14, 15, 16, 17, 19,
Y0 to Y19Data outputs
20, 21, 23, 24, 26, 27
4, 11, 18, 25, 32, 35, 39,
46, 53
7, 22, 35, 50 V
1 OE
29 LE
GND Ground (0V)
Positive supply voltage
CC
Output enable input
(active LOW)
Latch enable input
(active LOW)
56 CP Clock input
55, 54, 52, 51, 49, 48,
47, 45, 44, 43, 42, 41,
40, 38, 37, 36, 34, 33,
A0 to A19Data inputs
31, 30
LOGIC SYMBOL
OE
CP
LE
LOGIC SYMBOL (IEEE/IEC)
OE
CP
LE
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
10
Y
11
Y
12
Y
13
Y
14
Y
15
Y
16
Y
17
Y
18
Y
19
74A VCM162836
1
56
29
2
0
3
1
5
2
6
3
8
4
9
5
10
6
12
7
13
8
14
9
15
16
17
19
20
21
23
24
26
27
EN1
2C3
C3
G2
1 ∇ 1
55
A
0
54
A
1
52
A
2
3D
51
A
3
49
A
4
48
A
5
47
A
6
45
A
7
44
A
8
43
A
9
42
A
10
41
A
11
40
A
12
38
A
13
37
A
14
36
A
15
34
A
16
33
A
17
31
A
18
30
A
19
A
0
D
Y
LE
CP
0
FUNCTION TABLE
INPUTS
SH00160
OE LE CP A
H X X X Z
TO THE 19 OTHER CHANNELS
L L X L L
L L X H H
SH00163
L H ↑ L L
L H ↑ H H
L H H X Y
L H L X Y
1
0
2
0
H = HIGH voltage level
L = LOW voltage level
X = Don’t care
Z = High impedance “off” state
↑ = LOW-to-HIGH level transition
NOTES:
1. Output level before the indicated steady-state input conditions
were established, provided that CP is high before LE goes low.
2. Output level before the indicated steady-state input conditions
were established.
1999 Sep 30
3
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