Philips 74AVC16374DGG Datasheet
INTEGRATED CIRCUITS
DATA SH EET
74AVC16374; 74AVCH16374
16-bit edge triggered D-type
flip-flop; 3-state
Objective specification
File under Integrated Circuits, IC24
1998 Dec 11
Philips Semiconductors Objective specification
16-bit edge triggered D-type flip-flop;
3-state
FEATURES
• Wide supply voltage range of 1.2 V to
3.6 V
• Complies with JEDEC standard
no. 8-1A/5/7
• CMOS low power consumption
• Input/Output tolerant up to 3.6 V
• DCO (Dynamic Controlled Output)
Circuit dynamically changes output
impedance, resulting in noise
reduction without speed degradation
• Low inductance multiple VCC and
GND pins for minimize noise and
ground bounce.
• All data inputs have bushold.
(only 74AVCH16374)
• Power off disables 74AVC16374;
74AVCH16374 outputs, permitting
Live Insertion.
DESCRIPTION
The 74AVC(H)16374 is a 16-bit edge
triggeredflip-flopfeaturingseparate D-type
inputsforeach flip-flopand3-State outputs
for bus oriented applications. Incorporates
bushold data inputs which eliminate the
need for external pull-up resistors to hold
unused inputs.
This product is designed to have an
extremely fast propagation delay and a
minimum amount of power consumption.
Toensurethehigh-impedanceoutputstate
during power up or power down, OE
n
should be tied to VCC through a pullup
resistor (Live insertion).
A Dynamic Controlled Output (DCO)
circuitry is implemented to support
termination line drive during transient. See
graphs at this page for typical curves.
The74AVCH16374consist of2sections of
eightedge-triggeredflip-flops.Aclock (CP)
input and an output enable (OE) are
provided per 8-bit section
QUICK REFERENCE DATA
GND = 0 V; T
SYMBOL PARAMETER CONDITIONS TYPICAL UNIT
/ t
t
PHL
PLH
F
max
C
I
C
PD
Notes
CPDis used to determine the dynamic power dissipation (PDin µW).
1.
= CPD× V
P
D
f
= input frequency in MHz;
i
f
= output frequency in MHz;
o
C
= output load capacitance in pF;
L
V
= supply voltage in V;
CC
∑ (C
× V
2. The condition is V
3. For type with bushold.
L
-50
-100
-150
-200
(V) OUTPUT CURRENT
-250
OH
I
-300
-350
-350
-300
-250
-200
-150
(V) OUTPUT CURRENT
OL
I
-100
-50
74AVC16374;
74AVCH16374
=25°C; tr=tf≤2.0 ns; CL=30pF.
amb
propagation delay
CP to Q
n
maximum clock
frequency
input capacitance 5.0 pF
power dissipation
capacitance per
buffer
2
× fi+ ∑ (CL× V
CC
2
× fo) = sum of outputs.
CC
= GND to V
I
0
1.8V
0
0
0
0.5 1.5
VCC= 1.8 V 1.9 ns
V
= 2.5 V 1.4 ns
CC
V
= 3.3 V 1.2 ns
CC
VCC= 1.8 V
V
= 2.5 V
CC
= 3.3 V
V
CC
(3)
(3)
(3)
320 MHz
400 MHz
500 MHz
notes 1 and 2
outputs enabled 22 pF
output disabled 5 pF
2
× fo) where:
CC
CC.
2.5V
3.3V
1.0 2.0 3.0
VOH(V) OUTPUT VOLTAGE
1.8V
1.0 2.0 3.00.5 1.5
VOL(V) OUTPUT VOLTAGE
2.5
2.5V
2.5
PMOS
3.5
3.3V
NMOS
3.5
1998 Dec 11 2
Philips Semiconductors Objective specification
16-bit edge triggered D-type flip-flop;
3-state
FUNCTION TABLE
See Note 1.
OPERATING MODES
Load and read register
(Hold mode)
Load register and disable outputs H
Note
1. H - HIGH voltage level;
h - HIGH voltage level one set-up time prior to the LOW-to-HIGH CP transition;
L - LOW voltage level;
l - LOW voltage level one set-up time prior to the LOW-to-HIGH CP transition;
X- don’t care;
Z - high impedance OFF-state;
↑- LOW-to-HIGH CP transition
INPUTS
OE CP Dn nY
L
L
H
↑
↑
↑
↑
L
h
I
h
INTERNAL
FLIP-FLOPS
74AVC16374;
74AVCH16374
OUTPUT
L
H
L
H
L
H
Z
Z
ORDERING AND PACKAGE INFORMATION
OUTSIDE NORTH
AMERICA
74AVC16374DGG −40 to +85 °C 48 TSSOP plastic SOT362-1
74AVCH16374DGG −40 to +85 °C 48 TSSOP plastic SOT362-1
PINNING
PIN SYMBOL DESCRIPTION
11
2, 3, 5, 6, 8, 9, 11 and 12 1Q
4, 10, 15, 21, 28, 34, 39 and 45 GND Ground (0 V)
7,18, 31 and 42 V
13, 14, 16, 17, 19, 20, 22 and 23 2Q0 to 2Q7 3-state flip-flop outputs
24 2
25 2CP Clock input
36, 35, 33, 32, 30, 29, 27 and 26 2D
47, 46, 44, 43, 41, 40, 38 and 37 1D
48 1CP Clock input
NORTH
AMERICA
TEMPERATURE
RANGE
OE Output enable input (active LOW)
to 1Q7 3-state flip-flop outputs
0
CC
OE Output enable input (active LOW)
to 2D7 Data inputs
0
to 1D
0
7
Positive supply voltage
Data inputs
PACKAGES
PINS PACKAGE MATERIAL CODE
1998 Dec 11 3
Philips Semiconductors Objective specification
16-bit edge triggered D-type flip-flop;
3-state
1OE
1Q
1Q
GND
1Q
1Q
V
CC
1Q
1Q
GND
1Q
1Q
2Q
2Q
GND
2Q
2Q
V
CC
2Q
2Q
GND
2Q
2Q
2OE
1
2
0
3
1
4
5
2
6
3
7
8
4
9
5
10
11
6
12
7
13
0
14
1
15
16
2
17
3
18
19
4
20
5
21
22
6
23
7
24
16374
48
1CP
1D
47
0
1D
46
1
45
GND
1D
44
2
43
1D
3
V
42
CC
41
1D
4
40
1D
5
39
GND
38
1D
6
37
1D
7
36
2D
0
35
2D
1
34
GND
33
2D
2
2D
32
3
31
V
CC
30
2D
4
29
2D
5
28
GND
27
2D
6
26
2D
7
25
2CP
74AVC16374;
74AVCH16374
124
1D
1D
1D
1D
1D
1D
1D
1D
2D
2D
2D
2D
2D
2D
2D
2D
1OE 2OE
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
1Q
1Q
1Q
1Q
1Q
1Q
1Q
1Q
2Q
2Q
2Q
2Q
2Q
2Q
2Q
2Q
2CP1CP
2
0
3
1
5
2
6
3
8
4
9
5
11
6
12
7
13
0
14
1
16
2
17
3
19
4
20
5
22
6
23
7
2548
47
46
44
43
41
40
38
37
36
35
33
32
30
29
27
26
Fig.1 Pin configuration.
1
1OE
1CP
2OE
2CP
1D0
1D1
1D2
1D3
1D4
1D5
1D6
1D7
2D0
2D1
2D2
2D3
2D4
2D5
2D6
2D7
1EN
48
C1
25
2EN
24
C2
247
1D
46
44
43
41
40
38
37
35
33
32
30
29
27
26
1
2D
2
1Q0
3
1Q1
5
1Q2
6
1Q3
8
1Q4
9
1Q5
11
1Q6
12
1Q7
1336
2Q0
14
2Q1
16
2Q2
17
2Q3
19
2Q4
20
2Q5
22
2Q6
23
2Q7
nD0
nCP
nOE
Fig.2 Logic symbol.
DQ
LATCH
1
CP
nQ0
Fig.3 IEEE/IEC logic symbol
1998 Dec 11 4
Fig.4 Logic Diagram.
Philips Semiconductors Objective specification
16-bit edge triggered D-type flip-flop;
3-state
V
CC
data
Input
74AVC16374;
74AVCH16374
To internal circuit
Fig.5 Bushold circuit.
1998 Dec 11 5
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