Philips 74AVC16373DGG, 74AVCH16373DGG Datasheet

DATA SH EET

Objective speciﬁcation File under Integrated Circuits, IC24

1998 Dec 11

INTEGRATED CIRCUITS

74AVC16373; 74AVCH16373

16-bit D-type transparent latch; 3-state

1998 Dec 11 2

Philips Semiconductors Objective speciﬁcation

16-bit D-type transparent latch; 3-state

74AVC16373;

74AVCH16373

FEATURES

• Wide supply voltage range of 1.2 V to

3.6 V

• Complies with JEDEC standard

no. 8-1A/5/7

• CMOS low power consumption

• Input/Output tolerant up to 3.6 V

• DCO (Dynamic Controlled Output)

Circuit dynamically changes output impedance, resulting in noise reduction without speed degradation

• Low inductance multiple VCC and

GND pins for minimize noise and ground bounce.

• All data inputs have bushold.

(only 74AVCH16373)

• Power off disables 74AVC16373;

74AVCH16373 outputs, permitting Live Insertion.

DESCRIPTION

The 74AVC(H)16373 is a 16-bit D-type transparentlatchfeaturingseparate D-type inputs for each latch and 3-State outputs for bus oriented applications. Incorporates bushold data inputs which eliminate the need for external pull-up resistors to hold unused inputs. One latch enable(LE) input and one enable OE are provided per 8-bit section.

This product is designed to have an extremely fast propagation delay and a minimum amount of power consumption.

Toensurethehigh-impedanceoutputstate during power up or power down, OE

n

should be tied to VCC through a pullup resistor (Live insertion).

A Dynamic Controlled Output (DCO) circuitry is implemented to support termination line drive during transient. See graphs at this page for typical curves.

The74AVCH16373consist of2sections of eight D-type transparant latches with 3-State true outputs.

QUICK REFERENCE DATA

GND = 0 V; T

amb

=25°C; tr=tf≤2.0 ns; CL=30pF.

Notes

1.

CPDis used to determine the dynamic power dissipation (PDin µW). P

D

= CPD× V

CC

2

× fi+ ∑ (CL× V

CC

2

× fo) where:

f

i

= input frequency in MHz;

f

o

= output frequency in MHz;

C

L

= output load capacitance in pF;

V

CC

= supply voltage in V;

∑ (C

L

× V

CC

2

× fo) = sum of outputs.

2. The condition is V

I

= GND to V

CC.

3. For type with bushold.

SYMBOL PARAMETER CONDITIONS TYPICAL UNIT

t

PHL

/ t

PLH

propagation delay Dn to Q

n

VCC= 1.8 V 1.6 ns V

CC

= 2.5 V 1.3 ns

V

CC

= 3.3 V 1.1 ns

t

PHL

/ t

PLH

propagation delay LE to Q

n

VCC= 1.8 V

(3)

1.7 ns

V

CC

= 2.5 V

(3)

1.4 ns

V

CC

= 3.3 V

(3)

1.2 ns

C

I

input capacitance 5.0 pF

C

PD

power dissipation capacitance per buffer

notes 1 and 2

outputs enabled 22 pF output disabled 5 pF

0

VOH(V) OUTPUT VOLTAGE

0

1.0 2.0 3.0

0.5 1.5

2.5

3.5

-300

-350

-200

-250

-150

-50

-100

I

OH

(V) OUTPUT CURRENT

PMOS

3.3V

2.5V

1.8V

0

VOL(V) OUTPUT VOLTAGE

1.0 2.0 3.00.5 1.5

2.5

3.5

0

-300

-200

-250

-150

-50

-100

I

OL

(V) OUTPUT CURRENT

NMOS

1.8V

3.3V

2.5V

-350

1998 Dec 11 3

Philips Semiconductors Objective speciﬁcation

16-bit D-type transparent latch; 3-state

74AVC16373;

74AVCH16373

FUNCTION TABLE

See Note 1.

Note

1. H - HIGH voltage level; h - HIGH voltage level one set-up time prior to the HIGH-to-LOW LO transition; L - LOW voltage level; l - LOW voltage level one set-up time prior to the HIGH-to-LOW LE transition; X- don’t care; Z - high impedance OFF-state.

ORDERING AND PACKAGE INFORMATION

PINNING

OPERATING MODES

INPUTS

INTERNAL

LATCHES

OUTPUT

OE LE Dn nY

enable and read register (Transparent mode)

L L

H H

L

H

L H

L

H

latch and read register (Hold mode)

L

H

L

H

L h

L H

L

H

latch register and disable outputs H

H

L L

I

h

L H

Z Z

OUTSIDE NORTH

AMERICA

NORTH

AMERICA

PACKAGES

TEMPERATURE

RANGE

PINS PACKAGE MATERIAL CODE

74AVC16373DGG −40 to +85 °C 48 TSSOP plastic SOT362-1 74AVCH16373DGG −40 to +85 °C 48 TSSOP plastic SOT362-1

PIN SYMBOL DESCRIPTION

11

OE Output enable input (active LOW)

2, 3, 5, 6, 8, 9, 11 and 12 1Q

0

to 1Q7 Data outputs 4, 10, 15, 21, 28, 34, 39 and 45 GND Ground (0 V) 7,18, 31 and 42 V

CC

Positive supply voltage 13, 14, 16, 17, 19, 20, 22 and 23 2Q0 to 2Q7 Data outputs 24 2

OE Output enable input (active LOW) 25 2LE Latch enable input (active HIGH) 36, 35, 33, 32, 30, 29, 27 and 26 2D

0

to 2D7 Data inputs

47, 46, 44, 43, 41, 40, 38 and 37 1D

0

to 1D

7

Data inputs

48 1LE Latch enable input (active HIGH)

1998 Dec 11 4

Philips Semiconductors Objective speciﬁcation

16-bit D-type transparent latch; 3-state

74AVC16373;

74AVCH16373

16373

1 2

1Q

0

2Q

0

1Q

4

2Q

4

3

1Q

1

2Q

1

1Q

5

2Q

5

4

GND

5

1Q

2

2Q

2

1Q

6

2Q

6

1Q

3

2Q

3

1Q

7

2Q

7

V

CC

8 9

10

GND

11 12 13 14 15

GND

16 17 18

V

CC

19 20 21

GND

22 23 24

25

2LE

26

27

28

GND

29

30

31

V

CC

32

33

34

GND

35

36

37

38

39

GND

40

41

42

V

CC

43

1D

3

2D

3

1D

7

2D

7

44

1D

2

2D

2

1D

6

2D

6

45

GND

46

1D

1

2D

1

1D

5

2D

5

47

1D

0

2D

0

1D

4

2D

4

48

1LE

1OE

2OE

Fig.1 Pin configuration.

1D

0

2D

0

1D

1

2D

1

1D

2

2D

2

1D

3

2D

3

1D

4

2D

4

1D

5

2D

5

1D

6

2D

6

1D

7

2D

7

47 46 44 43 41 40 38 37 36 35 33 32 30 29 27 26

2Q

0

1Q

0

2Q

1

1Q

1

2Q

2

1Q

2

2Q

3

1Q

3

2Q

4

1Q

4

2Q

5

1Q

5

2Q

6

1Q

6

2Q

7

1Q

7

2 3 5 6 8 9 11 12 13 14 16 17 19 20 22 23

2LE1LE

2548

124

1OE 2OE

Fig.2 Logic symbol.

2EN

C3

1EN

C4

48 25

1

24

3D

1

247

46

3

44

5

43

6

41

8

40

9

38

11

37

12

4D

2

1336

35

14

33

16

32

17

30

19

29

20

27

22

26

23

1LE 2OE

1OE

2LE

1D0 1D1 1D2 1D3 1D4 1D5 1D6 1D7 2D0 2D1

2D3 2D4 2D5 2D6

2D2

2D7

1Q0 1Q1 1Q2 1Q3 1Q4 1Q5 1Q6 1Q7 2Q0 2Q1

2Q3 2Q4 2Q5 2Q6

2Q2

2Q7

Fig.3 IEEE/IEC logic symbol

nD

0

nLE nOE

LATCH

1

DQ

LE

nQ

0

Fig.4 Logic Diagram.

1998 Dec 11 5

Philips Semiconductors Objective speciﬁcation

16-bit D-type transparent latch; 3-state

74AVC16373;

74AVCH16373

V

CC

data

Input

To internal circuit

Fig.5 Bushold circuit.