Philips 74AVC16244DGG, 74AVCH16244DGG Datasheet

INTEGRATED CIRCUITS

DATA SH EET

74AVC16244; 74AVCH16244

16-bit buffer/line driver; 3-state

Objective specification
File under Integrated Circuits, IC24

1998 Dec 11

Philips Semiconductors Objective specification

16-bit buffer/line driver; 3-state

FEATURES

• Wide supply voltage range of 1.2 V to

3.6 V

• Complies with JEDEC standard

no. 8-1A/5/7

• CMOS low power consumption

• Input/Output tolerant up to 3.6 V

• DCO (Dynamic Controlled Output)

Circuit dynamically changes output
impedance, resulting in noise
reduction without speed degradation

• Low inductance multiple VCC and

GND pins for minimize noise and
ground bounce.

• All data inputs have bushold.

(only 74AVCH16244)

• Power off disables 74AVC16244;

74AVCH16244 outputs, permitting
Live Insertion.

DESCRIPTION

The 74AVC(H)16244 is a 16-bit
non-inverting buffer/line driver with 3-state
outputs. The device can be used as four
4-bit buffers, two 8-bit buffers or one 16-bit
buffer. The 3-state outputs are controlled
by the output enable input 1OE and 2OE.
A HIGH on nOE causes the outputs to
assume a high impedance OFF-state.

This product is designed to have an
extremely fast propagation delay and a
minimum amount of power consumption.

Toensurethehigh-impedance outputstate
during power up or power down, OE
should be tied to VCC through a pull up
resistor (Live insertion).

A Dynamic Controlled Output (DCO)
circuitry is implemented to support
termination line drive during transient. See
graphs at this page for typical curves.

n

74AVC16244;

74AVCH16244

QUICK REFERENCE DATA

GND = 0 V; T

SYMBOL PARAMETER CONDITIONS TYPICAL UNIT

/ t

t

PHL

PLH

/ t

t

PHL

PLH

C

I

C

PD

Notes

CPDis used to determine the dynamic power dissipation (PDin µW).

1.

= CPD× V

P

D

f

= input frequency in MHz;

i

f

= output frequency in MHz;

o

C

= output load capacitance in pF;

L

V

= supply voltage in V;

CC

∑ (C

× V

2. The condition is V

3. For type with bushold.

L

0

-50

-100

-150

-200

(V) OUTPUT CURRENT

-250

OH

I

-300

-350

-350

-300

-250

-200

=25°C; tr=tf≤2.0 ns; CL=30pF.

amb

propagation delay
Anto Y

n

propagation delay

to Y

A

n

n

VCC= 1.8 V 1.5 ns
V

= 2.5 V 1.1 ns

CC

V

= 3.3 V 1.0 ns

CC

VCC= 1.8 V
V

= 2.5 V

CC

= 3.3 V

V

CC

(3)
(3)
(3)

1.5 ns

1.1 ns

1.0 ns
input capacitance 5.0 pF
power dissipation

capacitance per
buffer

2

× fi+ ∑ (CL× V

CC

2

× fo) = sum of outputs.

CC

= GND to V

I

1.8V

0

0.5 1.5

notes 1 and 2

outputs enabled 20 pF
output disabled 4 pF

2

× fo) where:

CC

CC.

2.5V

3.3V

1.0 2.0 3.0

VOH(V) OUTPUT VOLTAGE

2.5

PMOS

3.3V

3.5

The 74AVCH16244 has active bushold
circuitry which is provided to hold unused
or floating data inputs at a valid logic level.
This feature eliminates the need for
external pull-up or pull-down resistors.

-150

(V) OUTPUT CURRENT

OL

I

-100

-50
0

0

1998 Dec 11 2

1.8V

1.0 2.0 3.00.5 1.5

VOL(V) OUTPUT VOLTAGE

2.5

2.5V

NMOS

3.5

Philips Semiconductors Objective specification

16-bit buffer/line driver; 3-state

74AVC16244;

74AVCH16244

FUNCTION TABLE

See Note 1.

INPUTS OUTPUTS

n

OE nA

n

LL L
LH H

HX Z

Note

1. H - HIGH voltage level;
L - LOW voltage level;
X- don’t care;
Z - high impedance OFF-state.

ORDERING AND PACKAGE INFORMATION

PACKAGES

OUTSIDE NORTH

AMERICA

NORTH

AMERICA

TEMPERATURE

RANGE

PINS PACKAGE MATERIAL CODE

74AVC16244DGG −40 to +85 °C 48 TSSOP plastic SOT362-1
74AVCH16244DGG −40 to +85 °C 48 TSSOP plastic SOT362-1

nY

n

PINNING

PIN SYMBOL DESCRIPTION

11
2, 3, 5 and 6 1Y

OE Output enable input (active LOW)

to 1Y

0

3

Data outputs
4, 10, 15, 21, 28, 34, 39 and 45 GND Ground (0 V)
7,18, 31 and 42 V
8, 9, 11 and 12 2Y
13, 14, 16 and 17 3Y
19, 20, 22 and 23 4Y
24 4
25 3
30, 29, 27 and 26 4A
36, 35, 33 and 32 3A
41, 40, 38 and 37 2A
47, 46, 44 and 43 1A
48 2

CC

to 2Y

0

3

to 3Y

0

3

to 4Y

0

3

OE Output enable input (active LOW)
OE Output enable input (active LOW)

to 4A

0

3

to 3A

0

3

to 2A

0

3

to 1A

0

3

OE Output enable input (active LOW)

Positive supply voltage

Data outputs

Data outputs

Data outputs

Data inputs

Data inputs

Data inputs

Data inputs

1998 Dec 11 3

Philips Semiconductors Objective specification

16-bit buffer/line driver; 3-state

1OE

1Y

1Y

GND

1Y
1Y

V

CC

2Y

2Y

GND

2Y
2Y

3Y

3Y

GND

3Y
3Y

V

CC
4Y
4Y

GND

4Y
4Y

4OE

1
2

0

3

1

4
5

2

6

3

7
8

0

9

1

10
11

2

12

3

16244

13

0

14

1

15
16

2

17

3

18
19

0

20

1

21
22

2

23

3

24

48

2OE
1A

47

0

1A

46

1

45

GND
1A

44

2

43

1A

3

V

42

CC

41

2A

0

40

2A

1

39

GND

38

2A

2

37

2A

3

36

3A

0

35

3A

1

34

GND

33

3A

2

32

3A

3

31

V

CC

30

4A

0

29

4A

1

28

GND

27

4A

2

26

4A

3

25

3OE

nA

nA

nA

nA

nOE

74AVC16244;

74AVCH16244

0

1

2

3

nY

nY

nY

nY

0

1

2

3

Fig.1 Pin configuration.

1

1OE
2OE

3OE
4OE

1A0
1A1
1A2
1A3
2A0
2A1
2A2
2A3
3A0
3A1
3A2

3A3
4A0
4A1
4A2
4A3

1EN

48

2EN

25

3EN

24

4EN

1

46 3
44
43 6
41
40 9
38
37

35 14
33
32 17
30
29 20
27
26

1

2

1

3

1

4

1

Fig.2 Logic symbol.

1Y0

247

1Y1

5

1Y2
1Y3

8

2Y0
2Y1
2Y2

11

2Y3

12
1336

3Y0
3Y1

16

3Y2
3Y3

19

4Y0
4Y1
4Y2

22

4Y3

23

data

Input

V

CC

To internal circuit

Fig.3 IEEE/IEC logic symbol. Fig.4 Bushold circuit.

1998 Dec 11 4