Philips 74AVC16244 Datasheet
INTEGRATED CIRCUITS
DATA SH EET
74AVC16244
16-bit buffer/line driver; 3-state
(3.6 V tolerant)
Product specification
Supersedes data of 1998 Dec 11
File under Integrated Circuits, IC24
1999 Nov 15
Philips Semiconductors Product specification
16-bit buffer/line driver; 3-state
(3.6 V tolerant)
FEATURES
• Wide supply voltage range from 1.2 to 3.6 V
• Complies with JEDEC standard no. 8-1A/5/7
• CMOS low power consumption
• Input/output tolerant up to 3.6 V
• Dynamic Controlled Output (DCO) circuit dynamically
changes output impedance,resulting in noise reduction
without speed degradation
• Low inductance multiple power and ground pins for
minimum noise and ground bounce
• Power off disables 74AVC16244 outputs, permittinglive
insertion.
74AVC16244
DESCRIPTION
The 74AVC16244 is a 16-bit non-inverting buffer/line
driverwith 3-state outputs. This devicecanbe used as four
4-bit buffers, two 8-bit buffers or one 16-bit buffer.
The 3-state outputs are controlled by the output enable
inputsnOE. A HIGH levelon input nOE causestheoutputs
to assume a high-impedance OFF-state.
This product is designed to have an extremely fast
propagation delay and a minimum amount of power
consumption.
To ensure the high-impedance output state during
power-up or power-down, input nOE should be tied to V
through a pull-up resistor (live insertion).
A DCO circuitry is implemented to support termination line
drive during transient (see Figs 1 and 2).
CC
handbook, halfpage
0
I
OH
(mA)
−100
−200
−300
012 4
1.8 V
2.5 V
3.3 V
3
VOH (V)
MNA506
300
handbook, halfpage
I
OL
(mA)
200
100
0
012 4
3.3 V
2.5 V
1.8 V
3
MNA507
VOL (V)
Fig.1 Outputcurrent as a function ofoutput voltage. Fig.2 Outputcurrent as a function ofoutput voltage.
1999 Nov 15 2
Philips Semiconductors Product specification
16-bit buffer/line driver; 3-state
74AVC16244
(3.6 V tolerant)
QUICK REFERENCE DATA
GND = 0 V; T
SYMBOL PARAMETER CONDITIONS TYP. UNIT
t
PHL/tPLH
C
I
C
PD
Notes
1. C
is used to determine the dynamic power dissipation (PDin µW).
PD
PD=CPD× V
fi= input frequency in MHz;
fo= output frequency in MHz;
CL= output load capacitance in pF;
VCC= supply voltage in Volts;
∑ (CL× V
2. The condition is VI= GND to VCC.
=25°C; tr=tf≤2.0 ns; CL=30pF.
amb
propagation delay
nAnto nY
n
input capacitance 5.0 pF
power dissipation
capacitance per buffer
2
× fi+ ∑ (CL× V
CC
2
× fo) = sum of outputs.
CC
2
× fo) where:
CC
VCC= 1.2 V 2.6 ns
V
= 1.5 V 1.8 ns
CC
V
= 1.8 V 1.7 ns
CC
= 2.5 V 1.3 ns
V
CC
V
= 3.3 V 1.1 ns
CC
notes 1 and 2
outputs enabled 34 pF
outputs disabled 1 pF
FUNCTION TABLE
See note 1.
n
OE nA
LLL
LHH
HXZ
Note
1. H = HIGH voltage level;
L = LOW voltage level;
X = don’t care;
Z = high-impedance OFF-state.
INPUTS OUTPUTS
n
nY
n
1999 Nov 15 3
Philips Semiconductors Product specification
16-bit buffer/line driver; 3-state
74AVC16244
(3.6 V tolerant)
ORDERING INFORMATION
TYPE NUMBER
TEMPERATURE RANGE PINS PACKAGE MATERIAL CODE
74AVC16244DGG −40 to +85 °C 48 TSSOP plastic SOT362-1
PINNING
PIN SYMBOL DESCRIPTION
11
2, 3, 5 and 6 1Y
OE output enable input (active LOW)
to 1Y
0
4, 10, 15, 21, 28, 34, 39 and 45 GND ground (0 V)
7, 18, 31 and 42 V
8, 9, 11 and 12 2Y
13, 14, 16 and 17 3Y
19, 20, 22 and 23 4Y
24 4
25 3
26, 27, 29 and 30 4A
32, 33, 35 and 36 3A
37, 38, 40 and 41 2A
43, 44, 46 and 47 1A
48 2
CC
to 2Y
0
to 3Y
0
to 4Y
0
OE output enable input (active LOW)
OE output enable input (active LOW)
to 4A
3
to 3A
3
to 2A
3
to 1A
3
OE output enable input (active LOW)
PACKAGE
3
3
3
3
0
0
0
0
data outputs
positive supply voltage
data outputs
data outputs
data outputs
data inputs
data inputs
data inputs
data inputs
1999 Nov 15 4
Philips Semiconductors Product specification
16-bit buffer/line driver; 3-state
(3.6 V tolerant)
handbook, halfpage
1OE
1Y
1Y
GND
1Y
1Y
V
CC
2Y
2Y
GND
2Y
2Y
3Y
3Y
GND
3Y
3Y
V
CC
4Y
4Y
GND
4Y
4Y
4OE
1
2
0
3
1
4
5
2
6
3
7
8
0
9
1
10
11
2
12
3
0
1
2
3
0
1
2
3
16244
13
14
15
16
17
18
19
20
21
22
23
24
MNA501
2OE
48
1A
47
0
1A
46
1
GND
45
1A
44
2
1A
43
3
V
42
CC
2A
41
0
2A
40
1
GND
39
2A
38
2
2A
37
3
3A
36
0
3A
35
1
GND
34
3A
33
2
3A
32
3
V
31
CC
4A
30
0
4A
29
1
GND
28
4A
27
2
4A
26
3
3OE
25
handbook, halfpage
handbook, halfpage
nA
0
nA
1
nA
2
nA
3
nOE
Fig.4 Logic symbol.
1
1EN
48
2EN
25
3EN
24
4EN
47
46
44
43
41
40
38
37
36
35
33
32
30
29
27
26
11
21
31
41
74AVC16244
nY
0
nY
1
nY
2
nY
3
MNA502
2
3
5
6
8
9
11
12
13
14
16
17
19
20
22
23
Fig.3 Pin configuration.
1999 Nov 15 5
MNA503
Fig.5 IEEE/IEC logic symbol.
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