Philips 74alvt16899 DATASHEETS

INTEGRATED CIRCUITS

74ALVT16899

2.5V/3.3V 18-bit latched transceiver with 16-bit parity generator/checker (3-State)

Product specification IC23 Data Handbook

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1998 Jun 30

Philips Semiconductors Product specification

SYMBOL

PARAMETER

CONDITIONS

UNIT

2.5V/3.3V 18-bit latched transceiver with 16-bit parity generator/checker (3-State)

FEATURES

•Symmetrical (A and B bus functions are identical)

•Selectable generate parity or ”feed-through” parity for A-to-B and

B-to-A directions

•Independent transparent latches for A-to-B and B-to-A directions

•Selectable ODD/EVEN parity

•Continuously checks parity of both A bus and B bus latches as

and ERRB

ERRA

•Open-collector ERR output

•Ability to simultaneously generate and check parity

•Can simultaneously read/latch A and B bus data

•Output capability: +64 mA/–32mA

•Latch-up protection exceeds 500mA per Jedec Std 17

•ESD protection exceeds 2000 V per MIL STD 883 Method 3015

and 200 V per Machine Model

•Power up 3-State

•Power-up reset

•No bus current loading when output is tied to 5 V bus

•Live insertion/extraction permitted

•Bus-hold data inputs eliminate the need for external pull-up

resistors to hold unused inputs

DESCRIPTION

The 74ALVT16899 is a high-performance BiCMOS product designed for V to 5V . The 74ALVT16899 is a 16-bit to 16-bit parity transceiver with separate transparent latches for the A bus and B bus. Either bus

operation at 2.5V or 3.3V with I/O compatibility up

74AL VT16899

can generate or check parity. The parity bit can be fed-through with no change or the generated parity can be substituted with the SEL input.

The 74ALVT16899 features independent latch enables for the A and B bus latches, a select pin for ODD/EVEN parity, and separate error signal output pins for checking parity.

FUNCTIONAL DESCRIPTION:

The 74ALVT16899 has three principal modes of operation which are outlined below. All modes apply to both the A-to-B and B-to-A directions.

Transparent latch, Generate parity, Check A and B bus parity:

Bus A (B) communicates to Bus B (A), parity is generated and passed on to the B (A) Bus as BPAR (APAR). If LEA and LEB are High and the Mode Select (SEL A0-A7 and B0-B7 can be checked and monitored by ERRA ERRB

. (Fault detection on both input and output buses.)

Transparent latch, Feed-through parity, Check A and B bus parity:

Bus A (B) communicates to Bus B (A) in a feed-through mode if SEL is High. Parity is still generated and checked as ERRA and ERRB and can be used as an interrupt to signal a data/parity bit error to the CPU.

Latched input, Generate/Feed-through parity, Check A (and B) bus parity:

Independent latch enables (LEA and LEB) allow other permutations of:

•Transparent latch / 1 bus latched / both buses latched

•Feed-through parity / generate parity

•Check in bus parity / check out bus parity / check in and out bus

parity

) is Low, the parity generated from

and

QUICK REFERENCE DATA

TYPICAL

2.5 V

2.0

2.2

9.8

7.0 3 3 pF 9 9 pF

3.3 V

1.5

1.7

7.8

5.1

PLH

PHL

PLH

PHL

C C I

CCZ

I/O

CONDITIONS

= 25°C; GND = 0V

amb

Propagation delay An to Bn or Bn to An

Propagation delay An to ERRA

Input capacitance VI = 0V or V

Output capacitance Outputs disabled; VO = 0V or V Quiescent supply current Outputs disabled 40 70 µA

CL = 50pF

ORDERING INFORMATION

PACKAGES TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA DWG NUMBER

56-Pin Plastic SSOP Type III –40°C to +85°C 74ALVT16899 AV16899 DL SOT371-1 56-Pin Plastic TSSOP Type II –40°C to +85°C 74ALVT16899 DGG AV16899 DGG SOT364-1

1998 Jun 30 853-2090-19651

Philips Semiconductors Product specification

2.5V/3.3V 18-bit latched transceiver with 16-bit parity generator/checker (3-State)

PIN CONFIGURATION

ODD/EVEN

1APAR

1ERRA

2ERRA

2APAR

1 2

OEA

1A0

GND

1A1

1A2

1A3 1B3

1A4

1A5

1A6

1A7

13 14 15

GND

16 17 18

2A7 2B7

2A6

2A5

2A4 2B4

2A3

2A2

2A1

GND

2A0

28 29

LEB

56 55 54 53 52

51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30

SV01731

SEL LEA 1B0 GND 1B1

1B2

1B4 V

1B5 1B6 1B7 1BPAR 1ERRB GND 2ERRB 2BPAR

2B6 2B5 V

2B3 2B2 2B1 GND 2B0 OEB

74ALVT16899

PIN DESCRIPTION

SYMBOL

1A0 - 1A7 2A0 - 2A7

1B0 - 1B7 2B0 - 2B7

1APAR 2APAR

1BPAR 2BPAR

ODD/EVEN 1 Parity select input (Low for EVEN parity)

OEA, OEB 2, 29

SEL 56 Mode select input (Low for generate)

LEA, LEB 55, 28 Latch enable inputs (transparent High)

1ERRA, 1ERRB 2ERRA, 2ERRB

GND 4, 15, 26, 31, 42, 53 Ground (0V)

1998 Jun 30

NUMBER

3, 5, 6, 7, 8, 10, 11, 12

27, 25, 24, 23, 22, 20, 19, 18 54, 52, 51, 50, 49, 47, 46, 45

30, 32, 33, 34, 35, 37, 38, 39

Latched A bus 3-State inputs/outputs

Latched B bus 3-State inputs/outputs

13, 17 A bus parity 3-State input/output

44, 40 B bus parity 3-State input/output

Output enable inputs (gate A to B, B to A)

14, 43,

16, 41

Error signal outputs (active-Low)

9, 21, 36, 48 Positive supply voltage

NAME AND FUNCTION

Philips Semiconductors Product specification

2.5V/3.3V 18-bit latched transceiver with 16-bit parity generator/checker (3-State)

LOGIC SYMBOL

3 5 6 7 8 10 11 12

1A0 1A1 1A2 1A3 1A4 1A5 1A6 1A7

55 28

29 OEB

LEA LEB

SEL

ODD/EVEN OEA

1B0 1B1 1B2 1B3 1B4 1B5 1B6 1B7

54 52 51 50 49 47 46 45

PARITY AND ERROR FUNCTION TABLE

INPUTS OUTPUTS

SEL ODD/EVEN

xPAR

(A or B)

H H H

H H L

H L H

H L L

L H H

L H L

L L H

L L L

H = High voltage level L = Low voltage level t = Transmit–if the data path is from A→B then ERRt r = Receive–if the data path is from A→B then ERRr is ERRB * Blocked if latch is not transparent

Σ of High

Inputs

Even

Odd

Even

Odd

Even

Odd

Even

Odd

Even

Odd

Even

Odd

Even

Odd

Even

Odd

1APAR

1ERRA 1ERRB

1BPAR

xPAR

(B or A)

H H

L L

H H

L L

is ERRA

14 43

ERRt ERRr*

27 25 24 23 22 20 19 18

2A0 2A1 2A2 2A3 2A4 2A5 2A6 2A7

55 28

LEA LEB

SEL

ODD/EVEN OEA

OEB

2B0 2B1 2B2 2B3 2B4 2B5 2B6 2B7

30 32 33 34 35 37 38 39

L L

H H

H Even H

L L

H H

H H Odd

H H

H H Even

H H

L Odd L

Mode

74ALVT16899

2APAR

2ERRA 2ERRB

2BPAR

PARITY MODES

Feed-through/check parity

Generate parity

16 41

SH00083

1998 Jun 30

Philips Semiconductors Product specification

2.5V/3.3V 18-bit latched transceiver with 16-bit parity generator/checker (3-State)

BLOCK DIAGRAM

9–bit

Transparent

Latch

LEA

A0 A1 A2 A3 A4 A5 A6 A7

APAR

Parity

Generator

9–bit

Output

Buffer

mux

9–bit

Output

Buffer

9–bit

Transparent

Latch

74ALVT16899

OEB

B0 B1 B2 B3 B4 B5 B6 B7 BPAR

OEA

SEL

ODD/

EVEN

mux

Parity

Generator

(1 of 2 parity blocks)

FUNCTION TABLE

INPUTS OPERATING MODE

OEB OEA SEL LEA LEB

H H X X X 3-State A bus and B bus (input A & B simultaneously) H L L L H B → A, transparent B latch, generate parity from B0 - B7, check B bus parity H L L H H B → A, transparent A & B latch, generate parity from B0 - B7, check A & B bus parity H L L X L B → A, B bus latched, generate parity from latched B0 - B7 data, check B bus parity H L H X H B → A, transparent B latch, parity feed-through, check B bus parity H L H H H B → A, transparent A & B latch, parity feed-through, check A & B bus parity

L H L H X A → B, transparent A latch, generate parity from A0 - A7, check A bus parity L H L H H A → B, transparent A & B latch, generate parity from A0 - A7, check A & B bus parity L H L L X A → B, A bus latched, generate parity from latched A0 - A7 data, check A bus parity L H H H L A → B, transparent A latch, parity feed-through, check A bus parity L H H H H A → B, transparent A & B latch, parity feed-through, check A & B bus parity L L X X X Output to A bus and B bus (NOT ALLOWED)

H = High voltage level L = Low voltage level X = Don’t care

LEB

ERRA

ERRB

SH00084

1998 Jun 30

Philips Semiconductors Product specification

DC out ut current

SYMBOL

PARAMETER

UNIT

2.5V/3.3V 18-bit latched transceiver with 16-bit parity

74ALVT16899

generator/checker (3-State)

ABSOLUTE MAXIMUM RATINGS

SYMBOL

OUT

CC IK

stg

DC supply voltage -0.5 to +4.6 V DC input diode current VI < 0 -50 mA DC input voltage

DC output diode current VO < 0 -50 mA DC output voltage

Storage temperature range -65 to +150 °C

NOTES:

1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability .

2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create ju nction temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150°C.

3. The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed.

PARAMETER CONDITIONS RATING UNIT

RECOMMENDED OPERATING CONDITIONS

∆t/∆v Input transition rise or fall rate; Outputs enabled 10 10 ns/V

amb

DC supply voltage 2.3 2.7 3.0 3.6 V Input voltage 0 5.5 0 5.5 V

High-level input voltage 1.7 2.0 V

Input voltage 0.7 0.8 V

High-level output current –8 –32 mA Low-level output current 8 32 Low-level output current; current duty cycle ≤ 50%; f ≥ 1kHz 24 64

Operating free-air temperature range –40 +85 –40 +85 °C

1, 2

-0.5 to +7.0 V

Output in Off or High state -0.5 to +7.0 V

Output in Low state 128

Output in High state -64

2.5V RANGE LIMITS 3.3V RANGE LIMITS MIN MAX MIN MAX

1998 Jun 30

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